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MMA8450Q rev 2, 03/2010 freescale semiconductor technical data an energy efficient solution by freescale this document contains certai n information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2010. all rights reserved. 3-axis, 8-bit/12-bit digital accelerometer the MMA8450Q is a smart low-power, three-axis, capacitive micromachined accelerometer featuring 12 bits of resolu tion. this accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins. embedded interrupt f unctions allow for overall power savings relieving the host processor from continuously polling data. the MMA8450Q?s embedded fifo buffer can be configured to log up to 32 samples of x,y and z-axis 12-bit (or 8-bit for faster download) data. the fifo enables a more efficient analysis of gestures and user programmable algorithms, ensuring no loss of data on a shared i 2 c bus, and enables system level power saving (up to 96% of the total power consumption sa vings) by allowing the applications processor to sleep while data is logged. there is access to both low pass filtered data as well as high pass f iltered data, which minimizes the data analysis required for jolt detection an d faster transitions. the MMA8450Q has user selectable full scales of 2g/4g/8g. the device can be configured to generate inertial wake-up interrupt si gnals from any combination of the configurable embedded functions allowing the MMA8450Q to monitor events and remain in a low power mode during periods of inactivity. the MMA8450Q is available in a 3 x 3 x 1 mm qfn package. features ? 1.71 v to 1.89 v supply voltage ? 2g/4g/8g dynamically selectable full-scale ? output data rate (odr) from 400 hz to 1.563 hz ?375 g/ hz noise at normal mode odr = 400 hz ? 12-bit digital output ?i 2 c digital output interface (operates up to 400 khz fast mode) ? programmable 2 interrupt pins for 8 interrupt sources ? embedded 4 channels of motion detection ? freefall or motion detection: 2 channels ? pulse detection: 1 channel ? transient (jolt) detection: 1 channel ? orientation (portrait/landscape) dete ction with hysteresis compensation ? automatic odr change for aut o-wake and return-to-sleep ? 32 sample fifo ? self-test ? 10,000g high shock survivability ? rohs compliant typical applications ? static orientation detection (portrai t/landscape, up/down, left/right, back/ front position identification) ? real-time orientation detection (virtual re ality and gaming 3d user position feedback) ? real-time activity analysis (pedometer step counting, freefall drop detection for hdd, dead-reckoning gps backup) ? motion detection for portable product power saving (aut o-sleep and auto-wake for cell phone, pda, gps, gaming) ? shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) ? user interface (menu scrolling by orientation change, tap detection for button replacement ordering information part number temperature range package drawing package MMA8450Qt -40c - +85c qfn-16 tray MMA8450Qr1 -40c - +85c qfn-16 tape and reel 1 gnd vdd scl nc int2 int1 gnd gnd sda sa0 vdd en nc nc nc gnd MMA8450Q 2 16 12 13 14 15 11 10 3 4 5 6 7 8 9 16 pin qfn 3mm x 3 mm x 1mm 16 pin qfn case 2077-01 MMA8450Q MMA8450Q: xyz-axis accelerometer 2g/4g/8g top and bottom view top view pin connections
sensors freescale semiconductor 2 MMA8450Q contents application notes for reference ............................................................................................... ................................................6 1 block diagram and pin description ............................................................................................ ......................................6 1.1 block diagram .............................................................................................................. ...............................................6 figure 1. block diagram ........................................................................................................ ......................................6 1.2 pin description ............................................................................................................ ................................................6 figure 2. direction of the detectable accelerations . ........................................................................... ........................6 figure 3. application diagram ............................ ...................................................................... ...................................7 table 1. pin description ....................................................................................................... .......................................7 1.3 soldering information ...................................................................................................... ............................................7 2 mechanical and electrical specifications ..................................................................................... ....................................8 2.1 mechanical characteristics ........................... ...................................................................... ........................................8 table 2. mechanical characteristics ............................................................................................ ...............................8 2.2 electrical characteristics ............................ ..................................................................... ............................................9 table 3. electrical characteristics @ vdd = 1.8 v, t = 25 c unless otherwise noted. ........................................... .. 9 2.3 i 2 c interface characteristic .................................................................................................... ...................................10 table 4. i 2 c slave timing values ......................................................................................................... ....................10 figure 4. i 2 c slave timing diagram ........................................................................................................ ..................11 2.4 absolute maximum ratings ....... ............................................................................................ ....................................11 table 5. maximum ratings .............. ......................................................................................... .................................11 table 6. esd and latch-up protection characteristics ........................................................................... .................11 3 terminology .................................................................................................................. .....................................................12 3.1 sensitivity ................................................................................................................ ..................................................12 3.2 zero-g offset .............................................................................................................. ...............................................12 3.3 self-test .................................................................................................................. ..................................................12 4 modes of operation ........................................................................................................... ................................................12 figure 5. MMA8450Q mode transition diagram ................. .............. .............. .............. .............. ............ ..................12 table 7. mode of operation description ................ ......................................................................... ...........................12 5 functionality ................................................................................................................ ......................................................13 5.1 device calibration ......................................................................................................... ............................................13 5.2 8-bit or 12-bit data ....................................................................................................... ..............................................13 5.3 internal fifo data buffer .................................................................................................. ........................................13 5.4 low power mode ......... .............. .............. .............. .............. ........... ........... ............ .......... ..........................................13 5.5 auto-wake/sleep mode .................................. ..................................................................... .....................................14 5.6 freefall and motion detection .............................................................................................. .....................................14 5.6.1 freefall detection ....................................................................................................... ....................................14 5.6.2 motion detection ......................................................................................................... ...................................14 5.7 transient detection ........................................................................................................ ...........................................14 5.8 orientation detection .................................. .................................................................... ...........................................15 figure 6. illustration of landscape-to-portrait transit ion .............. .............. .............. .............. ............ .....................15 figure 7. illustration of portrait-to-landscape transition ............ ......................................................... .....................15 figure 8. illustration of z-tilt a ngle lockout transition ...................................................................... .......................15 figure 9. landscape/portrait orientation ................. ...................................................................... ...........................16 5.9 interrupt register configuratio ns .......................................................................................... ....................................16 figure 10. system interrupt generation block diagram ... ........................................................................ .................16 5.10 serial i 2 c interface ................................................................................................................... .................................17 table 8. serial interface pin description ............... ....................................................................... .............................17 5.10.1 i 2 c operation ................................................................................................................... ..............................17 table 9. i 2 c address selection table ................................. .................................................................... ..................17 single byte read .............................................................................................................. ...........................................17 multiple byte read ...... .............. .............. .............. .............. .............. ........... ............ ......... ...........................................18 single byte write ............................................................................................................. .............................................18 multiple byte write ........................................................................................................... ............................................18 table 10. i 2 c device address sequence ..................................................................................................... .............18 figure 11. i 2 c timing diagram .............................................................................................................. ....................18
sensors freescale semiconductor 3 MMA8450Q 6 register descriptions ........................................................................................................ ...............................................19 table 11. register address map ................................................................................................. ..............................19 6.1 data registers ............................................................................................................. ..............................................21 0x00, 0x04, 0x0b: status registers ............................................................................................ .............................21 alias for dr_status (0x0b) or f_status (0x10) ....... .......................................................................... ..................21 0x00, 0x04, 0x0b status: data status registers (read only) .................................................................... ..21 table 12. status description ................................................................................................... ..............................21 0x01, 0x02, 0x03: out_msb 8-bit xyz data registers . ........................................................................... .................22 0x01 out_x_msb: x_msb register (read only) ............. ....................................................................... .........22 0x02 out_y_msb: y_msb register (read only) ............. ....................................................................... .........22 0x03 out_z_msb: z_msb register (read only) ............. ....................................................................... .........22 0x05 - 0x0a: out_msb and out_lsb 12-bit xyz data regi sters .................................................................... .......22 0x05 out_x_lsb: x_lsb register (read only) ............ ........................................................................ ...........22 0x06 out_x_msb: x_msb register (read only) ............. ....................................................................... .........22 0x07 out_y_lsb: y_lsb register (read only) ............ ........................................................................ ...........22 0x08 out_y_msb: y_msb register (read only) ............. ....................................................................... .........22 0x09 out_z_lsb: z_lsb register (read only) ............ ........................................................................ ...........22 0x0a out_z_msb: z_msb register (read only) .......... .......................................................................... .........22 0x0c - 0x0e: out_x_delta, out_y_delt a, out_z_delta ac data registers . ...............................................23 0x0c out_x_delta: ac x 8-bit data register (read on ly) ........................................................................ ... 23 0x0d out_y_delta: ac y 8-bit data register (read on ly) ........................................................................ ... 23 0x0e out_z_delta: ac z 8-bit data register (read only ) ........................................................................ ....23 0x0f: who_am_i device id register ..................... ........................................................................ ............................23 0x0f who_am_i: device id register (read only) ......... .............. .............. ........... ........... ............ .......... ...........23 6.2 32 sample fifo ............................................................................................................. ...........................................23 0x10: f_status fifo status register ........................................................................................... ...........................23 0x10 f_status: fifo status register (read only) ....... .............. .............. ............ ........... ........... ........... .....23 table 13. fifo flag event description .......................................................................................... ...........................23 table 14. fifo sample count description ........................................................................................ .......................24 0x11: f_8data 8-bit fifo data ................................................................................................. ................................24 0x11 f_8data: 8-bit fifo data register points to regist er 0x01 (read only) ................................................24 0x12: f_12data 12-bit fifo data ............................................................................................... ..............................24 0x12 f_12data: 12-bit fifo data register points to regi ster 0x05 (read only) ............................................24 0x13: f_setup fifo setup register ..................... ........................................................................ ............................24 0x13 f_setup: fifo setup register (read/write) ........ .............. .............. ........... ........... ............ .......... ...........24 0x14: sysmod system mode register ............ .............. .............. .............. .............. .............. ........... .........................25 0x14 sysmod: system mode register (read only) ......... ........................................................................ ........25 table 15. sysmod description ........... .............. .............. .............. .............. ........... ............ ......... .............................25 table 16. f_setup description .................................................................................................. .............................25 0x15: int_source system interrupt status register .. ........................................................................... ..................26 0x15 int_source: system interrupt status register (read only) ........... .............. .............. .............. ............ .26 table 17. int_source description ... .............. .............. .............. .............. .............. ........... ........... .........................26 0x16: xyz_data_cfg sensor data configuration register ......................................................................... ............27 0x16 xyz_data_cfg: sensor data configuration register (read/write) .......................................................27 table 18. xyz_data_cfg description ........................ ...................................................................... ..................... 27 0x17: hp_filter_cutoff high pass filter register .............................................................................. .................27 0x17 hp_filter_cutoff: high pass filter register (read/wr ite) ................................................................. 27 table 19. hp_filter_cutoff setting options ............ ......................................................................... ................27 6.3 portrait/ landscape embedded function registers ...... .............. .............. .............. .............. .............. ......................27 0x18: pl_status portrait/landscape st atus register ............................................................................ ..................27 0x18 pl_status register (read only) ...................... ..................................................................... .................27 0x19: pl_pre_status portrait/landscape previous data st atus register .......................................................... ... 28 0x19 pl_pre_status register (read only) ....................................................................................... ............28 0x1a: pl_cfg portrait/landscape conf iguration register ........................................................................ .................28 0x1a pl_cfg register (read/write) ............................................................................................. .....................28 table 20. pl_cfg register description .......................................................................................... .........................28 0x1b: pl_count portrait landscape debounce register ........................................................................... ..............28 0x1b pl_count register (read/write) ................... ........................................................................ .................28 table 21. pl_status register description .............. ......................................................................... .....................28 table 22. pl_count relationship with the odr ................................................................................... .................29
sensors freescale semiconductor 4 MMA8450Q 0x1c: pl_bf_zcomp back/front and z compensation register ...................................................................... ........29 0x1c: pl_bf_zcomp register (read/wr ite) ....................................................................................... .............29 table 23. pl_bf_zcomp description .............................................................................................. .......................29 table 24. back/front orientation definitions ................................................................................... ..........................29 0x1d - 0x1f: pl_p_l_ths_reg1, 2, 3 port rait-to-landscape threshold registers .................................................2 9 0x1d pl_p_l_ths_reg1 register (read/write) .................................................................................... ..........29 table 25. pl_p_l_ths_reg1 description .......................................................................................... ....................29 0x1e pl_p_l_ths_reg2 register (read/write) ........... ......................................................................... ..........29 table 26. pl_p_l_ths_reg2 description .......................................................................................... ....................29 0x1f pl_p_l_ths_reg3 register (read/write) .................................................................................... ..........29 0x20 - 0x22 pl_l_p_ths_reg1, 2, 3 landscape-to-portrait th reshold registers . .............. ............... ........... .......... 30 0x20 pl_l_p_ths_reg1 register (read/write) .............. ...................................................................... ..........30 table 27. pl_l_p_ths_reg1 description .......................................................................................... ....................30 0x21 pl_l_p_ths_reg2 register (read/write) .............. ...................................................................... ..........30 table 28. pl_l_p_ths_reg2 description .......................................................................................... ....................30 0x22 pl_l_p_ths_reg3 register (read/write) .............. ...................................................................... ..........30 table 29. pl_l_p_ths_reg3 description .......................................................................................... ....................30 table 30. landscape-to-portrait trip angle thresholds lo ok-up table ............................................................ ........30 table 31. pl_p_l_ths_reg3 description .......................................................................................... ....................30 table 32. portrait-to-landscape trip angle thresholds lo ok-up table ............................................................ ........30 6.4 freefall & motion detection registers ................ ...................................................................... .................................31 0x23: ff_mt_cfg_1 freefall and motion configuration regi ster 1 ................................................................ ...........31 0x23 ff_mt_cfg_1 register (read/write) ........................................................................................ ...............31 table 33. ff_mt_cfg_1 description ........................ ...................................................................... ........................31 0x24 ff_mt_src_1 register (read only) .................. ....................................................................... .......................32 0x24: ff_mt_src_ freefall and motion source register (0 x24) ......... .............. ........... ............ ........... .......... ... 32 table 34. ff_mt_src_1 description ........................ ...................................................................... ........................32 0x25: ff_mt_ths_1 freefall and motion threshold 1 regist er .................................................................... ............32 0x25 ff_mt_ths_1 register (read/write) ........................................................................................ ...............32 table 35. ff_mt_ths_1 description .............................................................................................. .........................32 figure 12. dbcntm bit function .......................... ....................................................................... .............................33 0x26: ff_mt_count_1 freefall motion count 1 register .. ........................................................................ ..............33 0x26 ff_mt_count_1 register (read/write) ...................................................................................... ............33 table 36. ff_mt_count_1 description ............................................................................................ .....................33 table 37. ff_mt_count_1 and ff_mt_count_2 relationship with the odr ..................................................33 0x27: ff_mt_cfg_2 freefall and motion configuration 2 re gister ................................................................ ...........34 0x27 ff_mt_cfg_2 register (read/write) ........................................................................................ ...............34 0x28: ff_mt_src_2 freefall and motion source 2 register ....................................................................... ..............34 0x28 ff_mt_src_2 register (read only) .................. ....................................................................... ...............34 0x29: ff_mt_ths_2 freefall and motion threshold 2 regist er .................................................................... ............34 0x29 ff_mt_ths_2 register (read/write) ........................................................................................ ...............34 0x2a: ff_mt_count_2 freefall and motion debounce 2 regi ster .......... .............. .............. ............... .............. .......34 0x2a ff_mt_count_2 register (read/write) .............. ........................................................................ ...........34 6.5 transient detection registers .............................................................................................. .....................................34 0x2b: transient_cfg transient configuration register .......................................................................... ..............34 0x2b transient_ cfg register (read/write) ........... .......................................................................... ............34 table 38. transient_ cfg description ........................................................................................... .....................34 0x2c: transient_src transient source register ...... ........................................................................... .................34 0x2c transient_src register (read only) ............... ........................................................................ ...........34 0x2d: transient_ths transient threshold register ..... ......................................................................... ................35 0x2d transient_ths register (read/write) ............ .......................................................................... ............35 table 39. transient_ths description ...................... ...................................................................... ......................35 0x2e: transient_count transient debounce register ..... ........................................................................ ...........35 0x2e transient_count register (read/write) ............ ........................................................................ ........35 table 40. transient_count description .......................................................................................... ..................35 table 41. transient_count relationship with the odr .. .......................................................................... .........35 table 42. transient_src description ..................... ....................................................................... .....................35 6.6 tap detection registers ................................................................................................... ........................................36 0x2f: pulse_cfg pulse configuration register ......... ......................................................................... .....................36 0x2f pulse_cfg register (read/write) .................... ...................................................................... ................36 table 43. pulse_cfg description .. .............................................................................................. ..........................36
sensors freescale semiconductor 5 MMA8450Q 0x30: pulse_src pulse source register ................ ......................................................................... ........................36 0x30 pulse_src register (read only) ...................... ..................................................................... .................36 table 44. tpulse_src description ............................................................................................... .........................36 0x31 - 0x33: pulse_thsx, y, z pulse threshold for x, y & z registers .......................................................... ........37 0x31 pulse_thsx register (read/write) ................... ...................................................................... ................37 table 45. pulse_thsx description ............................................................................................... .........................37 0x32 pulse_thsy register (read/write) ................... ...................................................................... ................37 table 46. pulse_thsy description ............................................................................................... .........................37 0x33 pulse_thsz register (read/writ e) ......................................................................................... ................37 table 47. pulse_thsz description ............................................................................................... .........................37 0x34: pulse_tmlt pulse time window 1 register ...... ........................................................................... .................37 0x34 pulse_tmlt register (read/write) ................ ......................................................................... ................37 table 48. time step for pulse time limit at odr and powe r mode ................................................................. ....37 0x35: pulse_ltcy pulse latency timer register ................................................................................. ...................38 0x35 pulse_ltcy register (read/write) ................ ......................................................................... ................38 table 49. time step for pulse latency at odr and power mode .................................................................... .....38 0x36: pulse_wind second pulse time window register .. .......................................................................... ............38 0x36 pulse_wind register (read/writ e) ............. .............. .............. .............. ............ ........... ........... ................38 table 50. time step for pulse detection window at odr and power mode .........................................................38 6.7 auto-sleep registers ............. .............. .............. .............. .............. ........... ............ ........... .........................................38 0x37: aslp_count auto-sleep inactivi ty timer register ......................................................................... ................38 0x37 aslp_count register (read/write) ............ .............. .............. .............. .............. ............ ......... ...............38 table 51. aslp_count description ............................................................................................... ........................38 table 52. aslp_count relationship with odr ............... ...................................................................... ................39 0x38: ctrl_reg1 system control 1 r egister ..................................................................................... ......................39 0x38 ctrl_reg1 register (read/write) .......................................................................................... .................39 table 53. ctrl_reg1 description ................................................................................................ ..........................39 table 54. sleep mode poll rate description ............ .............. .............. ........... ........... ........... ............ ........................39 table 55. system output data rate selection ......... ........................................................................... ......................39 table 56. full scale selection ............................ ..................................................................... ..................................40 0x39: ctrl_reg2 system control 2 r egister ..................................................................................... ......................40 0x39 ctrl_reg2 register (read/write) .......................................................................................... .................40 table 57. ctrl_reg2 description ................................................................................................ ..........................40 0x3a: ctrl_reg3 interrupt control register ........... ......................................................................... ........................40 0x3a ctrl_reg3 register (read/write) .................... ...................................................................... ................40 table 58. ctrl_reg3 description ................................................................................................ ..........................41 0x3c: ctrl_reg5 register (read/writ e) .............. .............. .............. .............. ........... ........... ........... .........................41 0x3c ctrl_reg5 register (read/write) .................... ...................................................................... ................41 table 59. interrupt enable register description ....... ......................................................................... ........................41 0x3c: ctrl_reg5 interrupt configuration register .... .......................................................................... ....................42 0x3c ctrl_reg5 register (read/write) .................... ...................................................................... ................42 table 60. interrupt configuration register description ......................................................................... ....................42 6.8 user offset correction registers .................... ....................................................................... ...................................42 0x3d: off_x offset correction x regi ster ...................................................................................... ...........................42 0x3d off_x register (read/write) ...................... ........................................................................ ......................42 table 61. off_x description .................................................................................................... ................................42 0x3e: off_y offset correctio n y register ...................................................................................... ...........................42 0x3e off_y register (read/write) ...................... ........................................................................ ......................42 table 62. off_y description .................................................................................................... ................................42 0x3f: off_z offset correction z register ...................................................................................... ............................42 0x3f off_z register (read/write) ...................... ........................................................................ ......................42 table 63. off_z description .................................................................................................... ................................42 appendix a .................................................................................................................... ............................................................43 table 64. MMA8450Q register map ................................................................................................ .........................43 table 65. accelerometer output data ............................................................................................ ...........................45 appendix b .................................................................................................................... ............................................................46 figure 13. distribution of pre board mounted devices tested in sockets (1 count = 3.9 mg ) ............ .............. .......46 figure 14. distribution of post board mounted devices (1 count = 3.9 mg) ....................................................... ......47 figure 15. 8g z-axis tcs ....................................................................................................... ...................................50 figure 16. 8g x-axis tco (mg/c) .. ............................................................................................. .............................51 figure 17. 8g y-axis tco (mg/c) .. ............................................................................................. .............................52 figure 18. 8g z-axis tco (mg/c) ........................ ....................................................................... .............................53 package dimensions ............................................................................................................ ................................................... 54
sensors freescale semiconductor 6 MMA8450Q application notes for reference the following is a list of freescale appl ication notes written for the MMA8450Q: ? an3915 , embedded orientation detection using the MMA8450Q ? an3916 , offset calibration of the MMA8450Q ? an3917 , motion and freefall detection using the MMA8450Q ? an3918 , high pass filtered data and transient detection using the MMA8450Q ? an3919 , MMA8450Q single/double and directional tap detection ? an3920 , using the 32 sample first in first out (fifo) in the MMA8450Q ? an3921 , low power modes and auto-wake/sleep using the MMA8450Q ? an3922 , data manipulation and basic settings of the MMA8450Q ? an3923 , MMA8450Q design checklist and board mounting guidelines 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. direction of the detectable accelerations 12-bit sda scl i 2 c embedded dsp functions c to v internal osc clock gen adc converter vdd vss x-axis transducer y-axis transducer z-axis transducer 32 data point configurable fifo buffer with watermark freefall and motion detection (2 channels) transient detection (i.e., fast motion, jolt) enhanced orientation with hysteresis and z-lockout shake detection through motion threshold tap and double tap detection auto-wake/auto-sleep configurabl e with debounce counter and multiple motion interrupts for control active mode auto-wake normal mode low power mode auto-sleep sleep mode (reduced sampling rate) 1 direction of the detectable acclerations (bottom view) 5 9 13 x y z 1 (top view)
sensors 7 freescale semiconductor MMA8450Q figure 3. application diagram when using MMA8450Q in applications, it is recommended that pin 1 and pin 14 (the vdd pins) be tied together. power supply decoupling capacitors (100 nf ceramic plus 4.7 f bulk, or a sing le 4.7 f ceramic) should be placed as near as possible to the pins 1 and 5 of the device. the sda and scl i 2 c connections are open drain and therefor e require a pull-up resistor as shown in figure 3 note: the above application diagram presents the recommended conf iguration for the MMA8450Q. for information on future products of this product family please review freescale application note, an3923, design checklist and board mounting guidelines of the MMA8450Q.this application note details the small modifications betw een the MMA8450Q and the next generation products. 1.3 soldering information the qfn package is compliant with the rohs standard. please refer to an3923. table 1. pin description pin # pin name description pin status 1 vdd power supply (1.8v only) input 2 nc/gnd connect to ground or non connection input 3 nc/gnd connect to ground or non connection input 4scl i 2 c serial clock open drain 5 gnd connect to ground input 6sda i 2 c serial data open drain 7 sa0 i 2 c least significant bit of the device address (0: $1c 0: $1d) input 8en device enable (1: i 2 c bus enabled; 0: shutdown mode) input 9 int2 inertial interrupt 2 output 10 gnd connect to ground input 11 int1 inertial interrupt 1 output 12 gnd connect to ground input 13 gnd connect to ground input 14 vdd power supply (1.8v only) input 15 nc internally not connected input 16 nc internally not connected input 0.1 f 1.8v 1.8v 1.8v 4.7k 4.7k 1 gnd vdd scl nc int2 int1 gnd gnd sda sa0 vdd en nc nc nc gnd MMA8450Q 2 16 12 13 14 15 11 10 3 4 5 6 7 8 9 4.7 f int1 int2 en sa0 scl sda
sensors freescale semiconductor 8 MMA8450Q 2 mechanical and elect rical specifications 2.1 mechanical characteristics table 2. mechanical characteristics @ vdd = 1.8 v, t = 25c unless otherwise noted. parameter test conditions symbol min typ max unit full scale measurement range fs[1:0] set to 01 fs 1.8 2 2.2 g fs[1:0] set to 10 3.6 4 4.4 fs[1:0] set to 11 7.2 8 8.8 sensitivity fs[1:0] set to 01 so 0.878 0.976 1.074 mg/digit fs[1:0] set to 10 1.758 1.953 2.148 fs[1:0] set to 11 3.515 3.906 4.296 sensitivity change vs. temperature (1) 1. before board mount. fs[1:0] set to 01 tcso 0.05 %/c typical zero-g level offset (2) 2. see appendix for distribution graphs. fs[1:0] set to 01 0g-off 40 mg fs[1:0] set to 10 fs[1:0] set to 11 typical zero-g offset post board mount (2), (3) 3. post board mount offset specification are based on an 8 layer pcb. fs[1:0] set to 01 0g-offbm 50 mg fs[1:0] set to 10 fs[1:0] set to 11 typical zero-g offset change vs. temperature (2) tcoff 0.5 mg/c non linearity best fit straight line fs[1:0] set to 01 nl 0.25 % fs fs[1:0] set to 10 0.5 fs[1:0] set to 11 1 self-test output change (4) 4. self-test in one direction only. these are appr oximate values and can change by 100 counts. fs[1:0] set to 01, x-axis vst -195 lsb fs[1:0] set to 01, y-axis -195 fs[1:0] set to 01, z-axis +945 output noise normal mode odr = 400 hz noise 375 g/ hz operating temperature range top -40 +85 c
sensors 9 freescale semiconductor MMA8450Q 2.2 electrical characteristics table 3. electrical characteristics @ v dd = 1.8 v, t = 25c unless otherwise noted . (1) 1. time to obtain valid data from standby mode to active mode. parameter test conditions symbol min typ max unit supply voltage vdd 1.71 1.8 1.89 v low power mode $39 ctrl_reg2: mod[0]=1 en = 1, odr = 1.563 hz i dd lp 27 a en = 1, odr = 12.5 hz 27 en = 1, odr = 50 hz 27 en = 1, odr = 100 hz 42 en = 1, odr = 200 hz 72 en = 1, odr = 400 hz 120 normal mode $39 ctrl_reg2: mod[0]=0 en = 1, odr = 1.563 hz i dd 42 a en = 1, odr = 12.5 hz 42 en = 1, odr = 50 hz 42 en = 1, odr = 100 hz 72 en = 1, odr = 200 hz 132 en = 1, odr = 400 hz 225 current consumption in shutdown mode en = 0 i dd sdn <1 a supply current drain in standby mode en = 1 and fs[1:0] = 00 i dd stby 3 a digital high level input voltage scl, sda, sa0, en vih 0.75*vdd v digital low level input voltage scl, sda, sa0, en vil 0.3*vdd v high level output voltage int1, int2 i o = 500 a voh 0.9*vdd v low level output voltage int1, int2 i o = 500 a vol 0.1*vdd v low level output voltage sda i o = 500 avols 0.1*vddv output data rate odr 0.9*odr odr 1.1*odr hz signal bandwidth bw odr/2 hz boot time from en = 1 to boot complete bt 1.55 ms turn-on time (1) ton 3/odr s
sensors freescale semiconductor 10 MMA8450Q 2.3 i 2 c interface characteristic table 4. i 2 c slave timing values (1) 1. all values referred to vih (min) and vil (max) levels. parameter symbol i 2 c standard mode i 2 c fast mode unit min max min max scl clock frequency f scl 0 100 0 400 khz bus free time between stop and start condition t buf 4.7 1.3 s repeated start hold time t hd;sta 40.6 s repeated start setup time t su;sta 4.7 0.6 s stop condition setup time t su;sto 40.6 s sda data hold time (2) 2. t hd;dat is the data hold time that is measur ed from the falling edge of scl, applies to data in transmission and the acknowledge. t hd;dat 0 (3) 3. a device must internally provi de a hold time of at least 300 ns for the sda si gnal (with respect to the vih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. (4) 4. the maximum t hd;dat could be 3.45 s and 0.9 s for standard-mode and fast-mode, but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this ma ximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. 0 (3) (4) s sda valid time (5) 5. t vd;dat = time for data signal from scl low to sda output (high or low, depending on which one is worse). t vd;dat 3.45 (4) 0.9 (4) s sda valid acknowledge time (6) 6. t vd;ack = time for acknowledgement signal from scl low to sd a output (high or low, depending on which one is worse). t vd;ack 3.45 (4) 0.9 (4) s sda setup time t su;dat 250 100 (7) 7. a fast-mode i 2 c device can be used in a standard-mode i 2 c system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r (max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. ns scl clock low time t low 4.7 1.3 s scl clock high time t high 40.6 s sda and scl rise time t r 1000 20 + 0.1c b (8) 8. c b = total capacitance of one bus line in pf. 300 ns sda and scl fall time (3)(5)(8)(9) 9. the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without e xceeding the maximum specified t f . t f 300 20 + 0.1c b (8) 300 ns pulse width of spikes on sda and scl that must be suppressed by input filter t sp 50 50 ns
sensors 11 freescale semiconductor MMA8450Q figure 4. i 2 c slave timing diagram 2.4 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. exposure to maximum rating conditions for extended periods may affect device reliability. table 5. maximum ratings rating symbol value unit maximum acceleration (all axes, 100 s) g max 10,000 g supply voltage vdd -0.3 to +2 v input voltage on any control pin (sa0, en, scl, sda) vin -0.3 to vdd + 0.3 v drop test d drop 1.8 m operating temperature range t op -40 to +85 c storage temperature range t stg -40 to +125 c table 6. esd and latch-up protection characteristics rating symbol value unit human body model hbm 2000 v machine model mm 200 v charge device model cdm 500 v latch-up current at t = 85c ? 100 ma this device is sensitive to mec hanical shock. improper handling can c ause permanent damage of the part or cause the part to otherwise fail. this is an esd sensitive, improper handl ing can cause permanent damage to the part.
sensors freescale semiconductor 12 MMA8450Q 3 terminology 3.1 sensitivity sensitivity describes the gain of the sens or and can be determined by applying a g acceleration to it, such as the earth's gravitational field. the sensitivity of the sensor can be dete rmined by subtracting the -1g a cceleration value from the +1g acceleration value and dividing by two. 3.2 zero-g offset zero-g offset (tyoff) describes the deviatio n of an actual output signal from the ideal output signal if no acceleration is pre sent. a sensor in a steady state on a horizontal surface will measure 0g in x-axis and 0g in y-axis whereas the z-axis will measure 1 g. the output is ideally in the middle of the dynamic range of t he sensor (content of out register s 0x00, data expressed as 2's complement number). a deviation from ideal value in this case is called zero-g offset. offset is to some extent a result of str ess on the mems sensor and therefore the offs et can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. 3.3 self-test self-test checks the transducer functionality without external mechanical stimulus. when se lf-test is activated, an electrostatic actuation force is applied to the sensor, simulating a small acceleration. in this case the sensor outputs will e xhibit a change in their dc levels which are related to the selected fu ll scale through the device sens itivity. when self-test is acti vated, the device output level is given by the algebraic sum of the si gnals produced by the acceleration acting on the sensor and by t he electrostatic test-force. 4 modes of operation figure 5. MMA8450Q mode transition diagram all register contents are preserved when transitioning from active to standby mode. some registers are reset when transitioning from standby to active. these are all noted in the de vice memory map register table. for more detail on how to us e the sleep and wake modes and how to transition between these modes, please refer to the functional ity section of this document. table 7. mode of operation description mode i 2 c bus state vdd en function description off powered down <1.5 v sensors 13 freescale semiconductor MMA8450Q 5functionality the MMA8450Q is a low-power, digital out put 3-axis linear accelerometer packaged in a qfn package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c serial interface. there are m any embedded features in this accelerometer with a very flexible interrupt routing scheme to 2 interrupt pins including: ? 8-bit or 12-bit data, high pass filtered data, 8-bit or 12-bit configurable 32 sample fifo ? low power and auto-wake/ sleep for co nservation of current consumption ? single and double pulse detection 1 channel ? motion detection and freefall 2 channels ? transient detection based on a high pass filter and settable threshold for detecting the change in acceleration above a threshold ? flexible user configurable portrait land scape detection algorithm addressing many use cases for screen orientation all functionality is available in 2g, 4g or 8g dynamic ranges. there are many configuration settings for enabling all the diffe rent functions. separate application notes have been provided to help configure the device for each embedded functionality. 5.1 device calibration the ic interface is factory calibrated for sensitivity and zero-g offset for each axis. the trim values are stored in non volat ile memory (nvm). on power-up, the trim pa rameters are read from nvm and applied to the circuitry. in normal use, further calibration in the end application is not nece ssary. however, the MMA8450Q allows the us er to adjust the zero-g offset for each axis after power-up, changing the default offset values. the user offset adjustments are stored in 6 volatile registers. for mo re information on device calibration, refer to freescale application note, an3916 . 5.2 8-bit or 12-bit data the measured acceleration data is stored in the ou tx_msb, outx_lsb, outy_msb, outy_lsb, outz_msb, and outz_lsb registers as 2?s complement 12-bit numbers. the most significant 8-bits of each axis are stored in out_x (y, z)_msb, so applications needing only 8-bit results can use these 3 registers and ignore out_x(y, z)_lsb. when the full-scale is set to 2g, the measurement range is -2g to +1.999g, and each lsb corresponds to 1g/1024 (0.98 mg) at 12-bits resolution. when the full-scale is set to 8g, the measurement range is -8g to +7.996g, and each lsb corresponds to 1g/256 (3.9 mg) at 12-bits resolution. the resolution is reduced by a factor of 16 if only the 8-bit results are used. for more information on the data manipulation between data formats and modes, refer to freescale application note, an3922. there is a device driver available that can be used with the sensor toolbox demo board (l fstbeb8450q) with this application note. 5.3 internal fifo data buffer MMA8450Q contains a 32 sample internal fifo data buffer minimizing traffic across the i2c bus. the fifo can also provide power savings of the system by allowing t he host processor/mcu to go into a sleep mode while the accelerometer independently stores the data, up to 32 samples per axis . the fifo can run at all output data rates. there is the option of accessing the ful l 12- bit data for accessing only the 8-bit data. when access speed is more important than high resolution the 8-bit data flush is a better option. the fifo contains three modes (fill buffer mode, circular bu ffer mode, and disabled) describ ed in the f_setup register 0x13. fill buffer mode collects the first 32 samples and asserts the overflow flag when the buffer is full. it does not collect anymore data until the buffer is read. this benefits data logging applic ations where all samples must be collected. the circular buffer mode allows the buffer to be filled and then new data replaces the oldes t sample in the buffer. the most recent 32 samples will be s tored in the buffer. this benefits situations where the processor is wa iting for an specific interrupt to signal that the data must b e flushed to analyze the event. the MMA8450Q fifo buffer also has a conf igurable watermark, allowing the processor to be interrupted after a configurable number of samples has filled in the buffer (1 to 32). for details on the configurations for the fifo buffer as well as more specific examples and application benefits, refer to freescale application note, an3920 . 5.4 low power mode the MMA8450Q can be set to a low power mode option to furthe r reduce the current consumpt ion of the device. when the low power mode is enabled, the device has access to all the conf igurable sampling rates and features as is available in the normal power mode. to set the device into low power mode, bit 0 in the system control register 2 (0x39) should be set (1) (this bit is cleared (0) for normal power mode). low power mode reduce s the current consumption by internally sleeping longer and averaging the data less. the low power mode is an additional feat ure that is independent of the sleep feature.th e sleep feature can also be used to reduce the current consumption by automat ically changing to a lower sample rate when no activity is detected. for more information on how to configure the MMA8450Q in low power mode and the power consumption benefits of low power mode and auto-wake/sleep with specific application examples, refer to freescale application note, an3921.
sensors freescale semiconductor 14 MMA8450Q 5.5 auto-wake/sleep mode the MMA8450Q can be configured to transition between sample ra tes (with their respective current consumption) based on five of the interrupt functions of the device. the advantage of using the auto-wake/sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the sleep mode (lower current) when the device does not require higher samp ling rates. auto-wake refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. this may also interrupt t he processor to transition from a sleep mode to a higher power mode. sleep mode occurs after the accelerometer has not detected an interrupt for longer than the user definable time-out period. the device will transition to the specified lower sample rate. it may also alert the processor to go into a lower power mode to save on current during this period of inactivity. the interrupts that can wake the device from sleep are the following: tap detection, orientation detection, motion/freefall1, motion/freefall2, and transient detection. the fifo can be configur ed to hold the data in the buffer until it is flushed if the fifo gate bit is set in register 0x3a but the fifo cannot wake the device from sleep. the interrupts that can keep the device from falling asleep are th e same interrupts that can wake the device with the addition of the fifo. if the fifo interrupt is enabled and data is being accessed continually servicing the interrupt then the device wi ll remain in the wake mode. refer to an3921, for more detailed information for configuring the auto-wake/sleep and for application examples of the power consumption savings. 5.6 freefall and motion detection MMA8450Q has flexible interrupt architecture for detecting free fall and motion with the two motion/freefall interrupt functions available. with two configurable interrupts for motion and free fall, one interrupt can be configured to detect a linear freefal l while the other can be configured to detect a spin motion. the combination of these two events can be routed to separate interrupts o r to the same interrupt pin to detect tumble which is the comb ination of spin with freefall. fo r details on the advantages of hav ing the two embedded functions of freefall and motion detection with specific application examples with recommended configuration settings, refer to freescale application note an3917. 5.6.1 freefall detection the detection of ?freefall? involv es the monitoring of the x, y, and z axes fo r the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. normally the usable threshold ranges are between 0 mg and 500 mg. 5.6.2 motion detection there are two programmable functions for motion (mff1 and mf f2). motion is configured using the high-g mechanism. motion is often used to simply alert the main processor that the devic e is currently in use. when the acceleration exceeds a se t threshold the motion interrupt is asserted. a motion can be a fa st moving shake or a slow moving tilt. this will depend on the threshold and timing values configured for the event. the motion detection function can analyze static acceleration changes or faster jolts. for example, to detect that an object is spinning, all three axes woul d be enabled with a threshold detection of > 2g. this condition would need to occur for a minimum of 100 ms to ensure that the event wasn't just noise. the timing value is set by a configurable debounce counter. the debounce counter acts lik e a filter to determine whet her the condition exists for configurable set of time (i.e., 100 ms or longer). 5.7 transient detection the MMA8450Q has a built in high pass filter . acceleration data goes through the high pass filter, eliminating the offset (dc) and low frequencies. the high pass filter cut-off frequency can be set by the user to four different frequencies which are dependent on the output data rate (odr). a higher cut-off freque ncy ensures the dc data or slower moving data will be filtered out, allowing only the higher frequencies to pass. the embedded transient detection function uses the high pass filtered data allowing the user to set the threshold and debounce counter. many applications use the accelerometer?s static acceleration readings (i.e., tilt) which measure the change in acceleration due to gravity only. these functions benefit from acceleration data being filtered from a lo w pass filter where high frequency data is considered noise. however, there are many functions where th e accelerometer must analyze dy namic acceleration. functions such as tap, flick, shake and step counting are based on the anal ysis of the change in the acceleration. it is simpler to inter pret these functions dependent on dynamic acceleration data when the static component has been remo ved. the transient detection function can be routed to either interrupt pin through bit 5 in ctrl_reg5 register (0x3c). registers 0x2b ? 0x2e are the dedicated transient detection configuration registers. for details on the benefits of the embedded transient detection function along with specific application examples and recommended confi guration settings, please refer to freescale application note, an3918.
sensors 15 freescale semiconductor MMA8450Q 5.8 orientation detection the MMA8450Q incorporates an advanced algorit hm for orientation detection (ability to detect all 6 orientations including portrait/landscape) with a large amount of configuration avai lable to provide extreme flexib ility to the system designer. the configurability also allows for the function to work differently for various modes of the end system. for example, the MMA8450Q orientation detection allows up to 10 selectable trip angles fo r portrait-to-landscape, up to10 selectable trip angles for the transition for landscape-to-portrait, and 4 selectable front/back tr ip angles. typically the desired hysteresis angle is 15 f rom a 45 trip reference point, resulting in |30| and |60| trip poi nts. the algorithm is robust enou gh to handle typical process va riation and uncompensated board mount of fset, however, it may result in slight angle variations. the MMA8450Q orientation detection algorithm confirms the reliability of the function with a configurable z-lock out angle. based on known functionality of linear accelerometers, it is not possible to rotate the device about the z-axis to detect chang e in acceleration at slow angular speeds. the angle at which the im age no longer detects the orientation change is referred to as th e ?z-lock- out angle?. the MMA8450Q orientation detection functi on has eight selectable1g-lockout thresholds; and there are 8 different settings for the z-angle lockout. the orientation detection function also considers when a device is experiencing acceleration above a set threshold not typical of orientation changes (i.e., when a person is jogging or due to acceleration changes from being on a bus or in a car). the scr een orientation should not interpret this as a change and the screen should lock in the last known valid position. this added featu re, called the 1g lockout threshold, enhances the orientation dete ction function and confirms the reliability of the algorithm for the system. the MMA8450Q allo ws for configuring the 1g lockout threshold from 1g up to 1. 35g (in incremen ts of 0.05g). for further information on the highly configurable embedded or ientation detection function, including recommendations for configuring the device to support various application use cases, refer to freescale application note, an3915 . figure 6 and figure 7 show the definitions of the trip angles going from landscape-to-portrait and then also from portrait-to- landscape. figure 6. illustration of land scape-to-portrait transition figure 7. illustratio n of portrait-to-l andscape tr ansition figure 8 illustrates the z-angle lockout region. when lifting the device up from the flat position it will be active for orientation detection as low as 25 from flat. this is user configurabl e. the default angle is 32 but it can be set as low as 25. figure 8. illustration of z-tilt angle lockout transition portrait landscape-to-portrait 90 trip angle = 60 0 landscape portrait portrait-to-landscape 90 trip angle = 60 0 landscape portrait normal 90 zlock = 32.142 0 landscape detection region lockout region
sensors freescale semiconductor 16 MMA8450Q figure 9 shows the device configuration in the 6 different orientat ion modes. these orientations are defined as the following: pu = portrait up, lr = landscape right, pd = portrait down, ll = landscape left, back and front. figure 9. landscape/portrait orientation there are several registers to configure t he orientation detection and are described in detail in the register setting section. 5.9 interrupt register configurations there are eight configurable interrupts in the MMA8450Q. thes e are auto-sleep, data ready, motion/freefall 1, motion/ freefall 2, transient, orientation detecti on, tap detection and the fifo events. t hese eight interrupt sources can be routed to one of two interrupt pins. the interrupt source must be enabled and configured. if the event flag is asserted because the event condition is detected, the corresponding interrupt pin, int1 or int2, will assert. figure 10. system interrupt generation block diagram top view pu earth gravity pin 1 xout @ 0g yout @ -1g zout @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ -1g yout @ 0g zout @ 0g ll pd lr side view front xout @ 0g yout @ 0g zout @ 1g back xout @ 0g yout @ 0g zout @ -1g auto-sleep fifo transient detect orientation detect pulse detect freefall /motion data ready func_en func_en func_en func_en func_en func_en func_en interrupt controller int_enable int1 int2 event flag 0 event flag 1 event flag 2 event flag 3 event flag 4 event flag 5 event flag 7 8 int_cfg 8 event flag 6
sensors 17 freescale semiconductor MMA8450Q 5.10 serial i 2 c interface acceleration data may be accessed through an i 2 c interface thus making the device particul arly suitable for direct interfacing with a microcontroller. the MMA8450Q features an interrupt si gnal which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in t he digital system that uses the device. the MMA8450Q may also be configured to generate other interrupt signals accordingly to the programmable embedded functi ons of the device for motion, freefall, transient, orientation, and tap. the registers embedded inside MMA8450Q are accessed through an i 2 c serial interface. to enable the i 2 c interface, the en pin (pin 8) must be tied high. when en is tied low, MMA8450Q is put into low power shutdown mode and communications on the i 2 c interface are ignored. the MMA8450Q is always in slave mode. the i 2 c interface may be used for communications between other i 2 c devices when en is tied low and the MMA8450Q does not clamp the i 2 c bus. there are two signals associated with the i 2 c bus; the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving th e data to/from the interface. external 4.7 k pull-up resistors connected to vdd are expected for sda and scl. when the bus is free both the lines are high. the i 2 c interface is compliant with fast mode (400 khz), and normal mode (100 khz) i 2 c standards ( ta b l e 4 ). 5.10.1 i 2 c operation the transaction on the bus is started through a start condition (start) signal. start condition is defined as a high to low transition on the data line while the scl line is held high. after start has been transmitted by the master, the bus is conside red busy. the next byte of data transmitted after start contains the slave address in the first 7 bits, and the eighth bit tells wh ether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the syst em compares the first seven bits after a start condition with its address. if they match, the devic e considers itself addressed by the master. the 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ack). the transmitter must release the sda line during the ack period. the re ceiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock period. the number of bytes transferred per transfer is unlimited. if a re ceiver can't receive another comp lete byte of data until it h as performed some other function, it can hold the clock line, scl low to force the trans mitter into a wait state. data transfer on ly continues when the receiver is ready for another byte and rel eases the data line. this delay ac tion is called clock stretching. a low to high transition on the sda line while the scl line is high is defined as a stop condition (stop). a data transfer is always terminated by a stop. a master may also issue a repeated start during a data transfer. the MMA8450Q expects repeated starts to be used to ran domly read from specific registers. the MMA8450Q's standard slave address is a choice between the two sequential addresses 0011100 and 0011101. the selection is made by the high and low logi c level of the sa0 (pin 7) input respec tively. the slave addresses are factory programmed and alternate addresses are available at customer request. the format is shown in table 9 . single byte read the MMA8450Q has an internal adc that can sample, convert and return sensor data on request. the transmission of an 8- bit command begins on the falling edge of scl. after the eight clock cycles are used to send the command, note that the data returned is sent with the msb first once the data is received. figure 11 shows the timing diagram for the accelerometer 8-bit i 2 c read operation. the master (or mcu) transm its a start condition (st) to the MMA8450Q , slave address ($1d), with the r/w bit set to ?0? for a write, and the MMA8450Q sends an acknowledg ement. then the master (or mcu) transmits the address of the register to read and the MMA8450Q sends an acknowledgement. th e master (or mcu) transmits a repeated start condition (sr) and then addresses the MMA8450Q ($1d) with t he r/w bit set to ?1? for a read from the previously selected register. the slave then acknowledges and transmits the data fr om the requested register. the master does not acknowledge (nak) it received the transmitted data, but transmits a stop condition to end the data transfer. table 8. serial interface pin description pin name pin description en device enable (1: i 2 c mode enabled; 0: shutdown mode) scl i 2 c serial clock sda i 2 c serial data sa0 i 2 c least significant bi t of the device address table 9. i 2 c address selection table slave address (sa0 = 0) slave address (sa0 = 1) comment 0011100 0011101 factory default
sensors freescale semiconductor 18 MMA8450Q multiple byte read when performing a multi-byte read or ?bur st read?, the MMA8450Q autom atically increments the received register address commands after a read command is received. therefore, after follow ing the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA8450Q ackno wledgment (ak) is received until a nack is received from the master followed by a stop conditio n (sp) signaling an end of transmission. single byte write to start a write command, the master trans mits a start condition (st) to the mma8 450q, slave address ($1d) with the r/w bit set to ?0? for a write, the MMA8450Q sends an acknowledgement. then the master (mcu) transmits the address of the register to write to, and the MMA8450Q sends an acknowledgement. then t he master (or mcu) transmits the 8-bit data to write to the designated register and the MMA8450Q sends an acknowledgement that it has received the data. since this transmission is complete, the master transmits a stop condi tion (sp) to the data transfer. the data sent to the MMA8450Q is now stored in the appropriate register. multiple byte write the MMA8450Q automatically increments th e received register address commands after a write command is received. therefore, after following the steps of a single byte write, mu ltiple bytes of data can be written to sequential registers afte r each MMA8450Q acknowledgment (ack) is received. figure 11. i 2 c timing diagram table 10. i 2 c device address sequence command [6:1] device address [0] sa0 [6:0] device address r/w 8-bit final value read 001110 0 0x1c 1 0x39 write 001110 0 0x1c 0 0x38 read 001110 1 0x1d 1 0x3b write 001110 1 0x1d 0 0x3a < single byte read > master st device address [6:0] w register address [7:0] sr device address [6:0] r nak sp slave ak ak ak data [7:0] < multiple byte read > master st device address [6:0] w register address [7:0] sr device address [6:0] r ak slave ak ak ak data [7:0] master ak ak nak sp slave data [7:0] data [7:0] data [7:0] < single byte write > master st device address [6:0] w register address [7:0] data [7:0] sp slave ak ak ak < multiple byte write > master st device address [6:0] w register address [7:0] data [7:0] data [7:0] slave ak ak ak ak legend st: start condition sp: stop condition nak: no acknowledge w: write = 0 sr: repeated start condition ak: acknowledge r: read = 1
sensors 19 freescale semiconductor MMA8450Q 6 register descriptions ta b l e 11 is the memory map of the mma8 450q.the user has access to all addresses from 0x00 to 0x3f. table 11. register address map name type register address auto-increment address default comment status (1)(2) r 0x00 0x01 00000000 addresses 0x00, 0x04, 0x 0b are aliases to the same register. data ready status information or fifo status information. out_x_msb (1)(2) r 0x01 0x02 0x01 output [7:0] are 8 msbs of 12-bit real-time sample. root pointer to xyz fifo 8-bit data. out_y_msb (1)(2) r 0x02 0x03 output [7:0] are 8 msbs of 12-bit real-time sample out_z_msb (1)(2) r0x03 0x00 output [7:0] are 8 msbs of 12-bit real-time sample status (1)(2) r 0x04 0x05 00000000 addresses 0x00, 0x04, 0x 0b are aliases to the same register. data ready status information or fifo status information. out_x_lsb (1)(2) r 0x05 0x06 0x05 output [3:0] are 4 lsbs of 12-bit sample. root pointer to xyz fifo 12-bit data. out_x_msb (1)(2) r 0x06 0x07 output [7:0] are 8 msbs of 12-bit real-time sample out_y_lsb (1)(2) r 0x07 0x08 output [3:0] are 4 lsbs of 12-bit real-time sample out_y_msb (1)(2) r 0x08 0x09 output [7:0] are 8 msbs of 12-bit real-time sample out_z_lsb (1)(2) r 0x09 0x0a output [3:0] are 4 lsbs of 12-bit real-time sample out_z_msb (1)(2) r0x0a 0x04 output [7:0] are 8 msbs of 12-bit real-time sample status (1)(2) r 0x0b 0x0c 00000000 addresses 0x00, 0x04, 0x 0b are aliases to the same register. data ready status information or fifo status information. out_x_delta (1)(2) r 0x0c 0x0d output 8-bit ac x-axis data out_y_delta (1)(2) r 0x0d 0x0e output 8-bit ac y-axis data out_z_delta (1)(2) r0x0e 0x0b output 8-bit ac z-axis data who_am_i (1) r 0x0f 0xc6 11000110 nwm programmable fixed device id no. f_status (1)(2) r 0x10 0x11 00000000 fifo status: no fifo event detected f_8data (1)(2) r0x11 0x11 output fifo status and 8-bit samples f_12data (1)(2) r0x12 0x12 output fifo status and 12-bit samples f_setup (1)(3) r/w 0x13 0x14 00000000 fifo setup sysmod (1)(2) r 0x14 0x15 output current system mode int_source (1)(2) r 0x15 0x16 output interrupt status xyz_data_cfg (1)(4) r/w 0x16 0x17 00000000 acceleration data event flag configuration hp_filter_cutoff 1,3 r/w 0x17 0x18 00000000 cutoff frequency is set to 4hz @ 400hz pl_status (1)(2) r 0x18 0x19 00000000 landscape/portrait orientation status pl_pre_status (1)(2) r 0x19 0x1a 00000000 landscape/portrait previous orientation pl_cfg (1)(4) r/w 0x1a 0x1b 10000011 landscape/portrait configuration. 1g lockout offset is set to default value of 1.15g. debounce counters are clear during invalid sequence condition. pl_count (1)(3) r/w 0x1b 0x1c 00000000 landscape/portrait debounce counter pl_bf_zcomp (1)(4) r/w 0x1c 0x1d 00000010 back-front trip threshold is 75. z-lockout angle is 32.14 pl_p_l_ths_reg1 (1)(4) r/w 0x1d 0x1e 00011010 portrait-to-landscape trip angle is 30
sensors freescale semiconductor 20 MMA8450Q note : auto-increment addresses which are not a simple increment are highlighted in bold . the auto-increment addressing is only enabled when device registers are read using i 2 c burst read mode. therefore the internal storage of the auto-increment address is clear whenever a stop-bit is detected. pl_p_l_ths_reg2 (1)(4) r/w 0x1e 0x1f 00100010 portrait-to-landscape trip angle is 30 pl_p_l_ths_reg3 (1)(4) r/w 0x1f 0x20 11010100 portrait-to-landscape trip angle is 30 pl_l_p_ths_reg1 (1)(4) r/w 0x20 0x21 00101101 landscape-to-portrait trip angle is 60 pl_l_p_ths_reg2 (1)(4) r/w 0x21 0x22 01000001 landscape-to-portrait trip angle is 60 pl_l_p_ths_reg3 (1)(4) r/w 0x22 0x23 10100010 landscape-to-portrait trip angle is 60 ff_mt_cfg_1 (1)(4) r/w 0x23 0x24 00000000 freefall/motion1 configuration ff_mt_src_1 (1)(2) r 0x24 0x25 00000000 freefall/motion1 event source register ff_mt_ths_1 (1)(3) r/w 0x25 0x26 00000000 freefall/motion1 threshold register ff_mt_count_1 (1)(3) r/w 0x26 0x27 00000000 freefall/motion1 debounce counter ff_mt_cfg_2 (1)(4) r/w 0x27 0x28 00000000 freefall/motion2 configuration ff_mt_src_2 (1)(2) r 0x28 0x29 00000000 freefall/motion2 event source register ff_mt_ths_2 (1)(3) r/w 0x29 0x2a 00000000 freefall/motion2 threshold register ff_mt_count_2 (1)(3) r/w 0x2a 0x2b 00000000 freefall/motion2 debounce counter transient_cfg (1)(4) r/w 0x2b 0x2c 00000000 transient configuration transient_src (1)(2) r 0x2c 0x2d 00000000 transient event status register transient_ths (1)(3) r/w 0x2d 0x2e 00000000 transient event threshold transient_count (1)(3) r/w 0x2e 0x2f 00000000 transient debounce counter pulse_cfg (1)(4) r/w 0x2f 0x30 00000000 ele, double_xyz or single_xyz pulse_src (1)(2) r 0x30 0x31 00000000 ea, double_xyz or single_xyz pulse_thsx (1)(3) r/w 0x31 0x32 00000000 x and y pulse threshold pulse_thsy (1)(3) r/w 0x32 0x33 00000000 z pulse threshold pulse_thsz (1)(3) r/w 0x33 0x34 00000000 z pulse threshold pulse_tmlt (1)(4) r/w 0x34 0x35 00000000 time limit for pulse pulse_ltcy (1)(4) r/w 0x35 0x36 00000000 latency time for 2nd pulse pulse_wind (1)(4) r/w 0x36 0x37 00000000 window time for 2nd pulse aslp_count (1)(4) r/w 0x37 0x38 00000000 counter setting for auto-sleep ctrl_reg1 (1)(4) r/w 0x38 0x39 00000000 odr = 400hz, standby mode. ctrl_reg2 (1)(4) r/w 0x39 0x3a 00000000 st = disabled, slpe = disabled, mods = normal mode. ctrl_reg3 (1)(4) r/w 0x3a 0x3b 00000000 ipol, pp_od ctrl_reg4 (1)(4) r/w 0x3b 0x3c 00000000 interrupt enable register ctrl_reg5 (1)(4) r/w 0x3c 0x3d 00000000 interrupt pin (int1/int2) map configuration off_x (1)(4) r/w 0x3d 0x3e 00000000 x-axis offset adjust off_y (1)(4) r/w 0x3e 0x3f 00000000 y-axis offset adjust off_z (1)(4) r/w 0x3f 0x0f 00000000 z-axis offset adjust 1. register contents are preser ved when transition from ?active? to ?standby? mode occurs. 2. register contents are reset when transiti on from ?standby? to ?active? mode occurs. 3. modification of this register?s contents can only occur when device is ?standby? mode 4. register contents can be modified anytime in ?standby? or ?active? mode. a write to th is register will cause a reset of the c orresponding internal system debounce counter. table 11. register address map
sensors 21 freescale semiconductor MMA8450Q 6.1 data registers the following are the data registers fo r the MMA8450Q. for more information on data manipulation of the MMA8450Q, refer to application note, an3922 . 0x00, 0x04, 0x0b: status registers . when fde bit found in register 0x16 (xyz_data_cfg), bit 7 is cleared (the fifo is not on) register 0x00, 0x04 and 0x0b should all be the same value and reflect the real-time status in formation of the x, y and z sample data. when fde is set (the fifo is on) register 0x00, 0x04 and 0x10 will have the same val ue and 0x0b will reflect the stat us of the transient data. the aliases allow the status register to be read easily before read ing the current 8-bit, 12-bit, or fifo sample data using the reg ister address auto-incrementing mechanism. zyxow is set whenever a new acceleration data is produced before completing the retrieval of the previous set. this event occurs when the content of at least one acceleration data regi ster (i.e., outx, outy, outz) has been overwritten. zyxow is cleared when the high-bytes of the acceleration data (outx_ms b, outy_msb, outz_msb) of all the active channels are read. zow is set whenever a new acceleration sample related to the z- axis is generated before the retr ieval of the previous sample. when this occurs the previous sample is overwritte n. zow is cleared anytime outz_msb register is read. yow is set whenever a new acceleration sample related to the y- axis is generated before the retr ieval of the previous sample. when this occurs the previous sample is overwritte n. yow is cleared anytime outy_msb register is read. xow is set whenever a new acceleration sample related to the x-ax is is generated before the retr ieval of the previous sample. when this occurs the previous sample is overwritte n. xow is cleared anytime outx_msb register is read. zyxdr signals that a new sample for any of the enabled channels is available. zyxdr is cleared when the high-bytes of the acceleration data (outx_msb, outy_msb, outz _msb) of all the enabled channels are read. zdr is set whenever a new acceleration sample related to the z- axis is generated. zd r is cleared anytime outz_msb register is read. in order to enable the monitoring and assertion of this bit, the zdr bit requires the z-axis event detection flag to b e enabled (bit zdefe = 1 inside xyz_data_cfg register). alias for dr_status (0x0b) or f_status (0x10) (read only) fde (fifo data enable bit 7, reg 0x16) setting alias status fde = 0 0x00 = 0x04 = dr_status (0x0b) fde = 1 0x00 = 0x04 = f_status (0x10) 0x00, 0x04, 0x0b status: data status registers (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zyxow zow yow xow zyxdr zdr ydr xdr table 12. status description zyxow x, y, z-axis data overwrite. default value: 0 0: no data overwrite has occurred 1: previous x, y, or z data was overwritten by new x, y, or z data before it was read zow z-axis data overwrite. default value: 0 0: no data overwrite has occurred 1: previous z-axis data was overwritten by new z-axis data before it was read yow y-axis data overwrite. default value: 0 0: no data overwrite has occurred 1: previous y-axis data was overwritten by new y-axis data before it was read xow x-axis data overwrite. default value: 0 0: no data overwrite has occurred 1: previous x-axis data was overwritten by new x-axis data before it was read zyxdr x, y, z-axis new data ready. default value: 0 0: no new set of data ready 1: a new set of data is ready zdr z-axis new data available. default value: 0 0: no new z-axis data is ready 1: a new z-axis data is ready ydr z-axis new data available. default value: 0 0: no new y-axis data ready 1: a new y-axis data is ready xdr z-axis new data available. default value: 0 0: no new x-axis data ready 1: a new x-axis data is ready
sensors freescale semiconductor 22 MMA8450Q ydr is set whenever a new acceleration sample related to the y- axis is available. ydr is cleared anytime outy_msb register is read. in order to enable the monitoring and assertion of this bit, the ydr bit requires the y-axis event detection flag to b e enabled (bit ydefe = 1 inside xyz_data_cfg register). xdr is set to 1 whenever a new acceleration sample related to the x-axis is available. xdr is cleared anytime outx_msb register is read. in order to enable the monitoring and assertion of this bit, the x dr bit requires the x-ax is to event detecti on flag to be enabled (bit xdefe = 1 inside xyz_data_cfg register). the zdr and zow flag generation requires the z-axis event flag gener ator to be enabled (zdefe = 1) in the xyz_data_cfg register. the ydr and yow flag generation requires the y-axis event flag gener ator to be enabled (ydefe = 1) in the xyz_data_cfg register. the xdr and xow flag generation requires the x-axis event flag generato r to be enabled (xdefe = 1) in the xyz_data_cfg register. the zyxdr and zyxow flag generation is requires the z-axis, y-axis, x-axis event flag generator to be enabled (zdefe = 1, ydefe = 1, xdefe = 1) in the xyz_data_cfg register. 0x01, 0x02, 0x03: out_msb 8-bit xyz data registers x, y and z-axis data is expressed as 2?s complement numb ers. the most significant 8-bits are stored together in out_x_msb, out_y_msb, out_z_msb so applications needing only 8-bit results can use these registers and can ignore the out_x_lsb, out_y_lsb, out_z_lsb. the status register 0x00, out_x_msb, out_y_m sb, out_z_msb are duplicated in the auto-incrementing address range of 0x00 to 0x03 to reduce reading the status followed by 8-bit axis data to a 4 byte sequence. 0x05 - 0x0a: out_msb and out_lsb 12-bit xyz data registers x, y and z-axis data is expressed as 2?s complement nu mbers. the status (0x04), out_x_lsb (0x05), out_x_msb (0x06), out_y_lsb (0x07), out_y_msb (0 x08), out_z_lsb(0x09), out_z_msb (0x0a) are stored in auto-incrementing address range of 0x04 to 0x0a to reduce reading the status followed by 12-bit axis data to 7 bytes. 0x01 out_x_msb: x_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 0x02 out_y_msb: y_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 0x03 out_z_msb: z_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4 0x05 out_x_lsb: x_lsb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 xd3 xd2 xd1 xd0 0x06 out_x_msb: x_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 0x07 out_y_lsb: y_lsb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000yd3yd2yd1yd0 0x08 out_y_msb: y_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 0x09 out_z_lsb: z_lsb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000zd3zd2zd1zd0 0x0a out_z_msb: z_msb register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4
sensors 23 freescale semiconductor MMA8450Q the sample data output registers store the current sample data if the fifo data output register driver is disabled, but if the fifo data output register driver is enab led,12 the sample data output registers point to the head of the fifo buffer which cont ains the previous 32 x, y, and z data samples. this applies for the 8-bit data and the 12-bit data. when the fde bit is set to logic 1, the f_8data (0x11) fifo root data pointer shares the same address location as the out_x_msb register (0x01); therefore all 8-bit acce sses of the fifo buffer data must use the i 2 c address 0x01. the f_12data (0x12) fifo root data pointer shares the same address location as the out_x_lsb register (0x05) ; therefore all 12-bit accesses of the fifo buffer data must use the i 2 c address 0x05. all reads to register address es 0x02, 0x03, 0x06, 0x07, 0x08, 0x09, and 0x0a returns a value of 0x00. 0x0c - 0x0e: out_x_delta, out_y_delta, out_z_delta ac data registers x, y, and z-axis 8-bit high pass filtered outp ut data is expressed as 2's complement numbers. the data is obtained from the output of the user definable high pass filter. the data cuts out the low frequency data, which is useful in that the offset dat a is removed. the value of the high pass filter cut off frequency is set in register 0x17. note: the out_x_delta, out_y_delta, out_z_delta registers store the hi gh pass filtered ?delta data? information regardless of the sta te of the fifo data output register driver bit. register 0x0b always reflects the status of the delta data. 0x0f: who_am_i device id register this register contains the device identifier which for MMA8450Q is set to 0xc6 by default. the value is factory programmed by a byte of nvm. a custom alternate value can be set by customer request. 6.2 32 sample fifo the following registers are used to configure the fifo. the fo llowing are the fifo registers for the MMA8450Q. for more information on the fifo please refer to an3920 . 0x10: f_status fifo status register the fifo status register is used to retrieve information abo ut the fifo. this register has a flag for the overflow and watermark. it also has a counter that can be read to obtain the number of samples stored in the buffer. the f_ovf and f_wmrk_flag flags remain asserted while the event source is still ac tive, but the user can clear the fifo interrupt bit flag in the interrupt source regist er (int_source) by reading the f_status register. therefore the f_ovf bit flag will remain asserted while the fi fo has overflowed and the f_wmrk_flag bit flag will remain asserted while the f_cnt value is greater than the f_wmrk value. 0x0c out_x_delta: ac x 8-bit data register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 0x0d out_y_delta: ac y 8-bit data register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 0x0e out_z_delta: ac z 8-bit data register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zd7zd6zd5zd4zd3zd2zd1zd0 0x0f who_am_i: device id register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11000110 0x10 f_status: fifo status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f_ovf f_wmrk_flag f_cnt5 f_cnt4 f_cnt3 f_cnt2 f_cnt1 f_cnt0 table 13. fifo flag event description f_ovf f_wmrk_flag event description 0 ? no fifo overflow events detected. 1 ? fifo event detected; fifo has overflowed. ? 0 no fifo watermark events detected. ? 1 fifo event detected; fifo sample count is greater than watermark value.
sensors freescale semiconductor 24 MMA8450Q f_cnt[5:0] bits indicate the number of acceleration samples currently stored in the fifo buffer. count 000000 indicates that the fifo is empty. 0x11: f_8data 8-bit fifo data f_8data provides access to the previous (up to) 32 samples of x, y, and z-axis acceleration data at 8-bit resolution. use f_12data to access the same fifo data at 12-bit resolution . the advantage of f_8data access is much faster download of the sample data, since it is represented by only 3 by tes per sample (out_x_msb, out_y_msb, and out_z_msb). all reads to address 0x01 returns the sensor sampled data in th e fifo buffer, 3 bytes per sample (one byte per axis), with the oldest samples first, in order out_x_msb, out_y_msb, and out_z_msb. when all samples indicated by the fifo_status register have been read from the fifo, su bsequent reads will return 0x00. since the fifo holds a maximum of 32 samples, a maximum of 3 x 32 = 96 data bytes of samples can be read. the fifo will not accumulate more sample data during an access to f_8data until a stop or repeated start occurs. the host application should initially perform a single byte read of the fifo status byte (address 0x10) to determine the status of the fifo and if it is determi ned that the fifo contains data sample(s), the fifo contents can also be read from register address location 0x01 or 0x05. 0x12: f_12data 12-bit fifo data f_12data provides access to the previous (up to) 32 samples of x, y, and z-axis acceleration data, at 12-bit resolution. use f_8data to access the same fifo data at 8-bit resolution. the advantage of f_8data access is much faster download of the sample data, since it is represented by only 3 bytes per sample (out_x_msb, ou t_y_msb, and out_z_msb). when the fde bit is set to logic 1, the f_12data fifo ro ot data pointer shares the same address location as the out_x_msb register (0x05); therefore all 12-bit a ccesses of the fifo buffer data must use the i 2 c register address 0x05. all reads to the register address 0x 02, 0x03, 0x06, 0x07, 0x 08, 0x09, and 0x0a return a value of 0x00. all reads from address (0x05) return the sample data, oldest samples first, in order out_ x_lsb out_x_msb, out_y_lsb, out_y_msb, out_z_lsb, and out_ z_msb. when all samples indicated by the f_ status byte have been read from the fifo, subsequent reads will return 0x00. since the fifo holds a maximu m of 32 samples, a maximum of 6 x 32 = 192 data bytes can be read. the fifo will not accumulate more sample data during an access to f_12data until a stop or repeated start occurs. 0x13: f_setup fifo setup register this setup register is used to configure the options for the fifo. the fifo can operate in 3 states which are defined in the mode bits. the watermark bits are configurable to set the number of samples of data to trigger the watermark event flag. the maximum number of samples is 32. for more information on the fifo configuration refer to an3920. table 14. fifo sample count description f_cnt[5:0] fifo sample counter. default value 00_0000. (00_0001 to 10_0000 indicates 1 to 32 samples stored in fifo 0x11 f_8data: 8-bit fifo data register points to register 0x01 (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 0x12 f_12data: 12-bit fifo data register points to register 0x05 (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 xd3 xd2 xd1 xd0 0x13 f_setup: fifo setup register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f_mode1 f_mode0 f_wmrk5 f_wmrk4 f_wmrk3 f_wmrk2 f_wmrk1 f_wmrk0
sensors 25 freescale semiconductor MMA8450Q a fifo sample count exceeding the waterma rk event does not stop the fifo from accepting new da ta. the fifo update rate is dictated by the selected system odr. in active mode the odr is set by the dr register in the ctrl_reg1 register and when auto-sleep is active the odr is set by the aslp_rate field in the ctrl_reg1 register. when a byte is read from the fifo buffer the oldest sample data in the fifo buffer is returned and also deleted from the front of the fifo buffer, while the fifo sample count is decremented by one. it is assumed that the host application shall use the i 2 c multi-read transaction to empty the fifo. the fifo mode can be changed while in the active state. the mode must first be disabled f_mode = 00 then the mode can be changed. 0x14: sysmod system mode register the system mode register indicates the current device operating mode. applications using th e auto-sleep/auto-wake mechanism should use this register to synchronize the applic ation with the device operatin g mode transitions. the system mode register also indicates the status of the nvm parity error and fifo gate error flags. the fifo gate is set in register 0x3a for the device configur ed for auto-wake/sleep mode to allow the buffer to preserve the data without automatically flushing. if the fifo buffer is not emptied before the arrival of the next sample, then the fgerr bi t in register 0x14 is asserted. the fgerr remains asserted as lo ng as the fifo buffer remains un- emptied. emptying the fifo buffer clears the fgerr bit. table 15. f_setup description bits description f_mode[1:0] (1)(2)(3) fifo buffer overflow mode. default value 0. 00: fifo is disabled. 01: fifo contains the most recent samples when overfl owed (circular buffer). oldest sample is discarded to be replaced by new sample. 10: fifo stops accepting new samples when overflowed. 11: not used. the fifo is flushed whenever the fifo is disabled, during an automatic odr change (auto-wake/sleep), or transitioning from ?standby? mode to ?active? mode. disabling the fifo (f_mode = 00) resets the f_ovf, f_wmrk_flag, f_cnt to zero. a fifo overflow event (i.e., f_cnt = 32) will assert the f_ovf flag and a fifo sample count equal to the sample count watermark (i.e., f_wmrk ) asserts the f_wmrk_flag event flag. f_wmrk[5:0] (2) fifo event sample count watermark. default value 00_0000. these bits set the number of fifo samples required to trigger a watermark interrupt. a fifo watermark event flag (f_wmk_flag) is raised when fifo sample count f_cnt[5:0] value is equal to the f_ wmrk[5:0] watermark. setting the f_wmrk[5:0] to 00_0000 will disabl e the fifo watermark event flag generation. 1. bit field can be written in active mode. 2. bit field can be written in standby mode. 3. the fifo mode (f_mode) cannot be switched between the two operational modes (01and 10) in active mode. 0x14 sysmod: system mode register (read only) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 perrfgerr0000sysmod1sysmod0 table 16. sysmod description perr nvm parity error flag bit. default value: 0. 0: no nvm parity error was detected. 1: nvm parity error detected. fgerr fifo gate error. default value: 0. 0: no fifo gate error detected. 1: fifo gate error was detected. sysmod system mode. default value: 00. 00: standby mode 01: wake mode 10: sleep mode
sensors freescale semiconductor 26 MMA8450Q 0x15: int_source system in terrupt status register in the interrupt source register the status of the various embedd ed features can be determined.the bits that are set (logic ?1? ) indicate which function has asserted an inte rrupt and conversely the bits that are cl eared (logic ?0?) indicate which function has not asserted or has de-asserted an interrupt. the interrupts are rising edge sensitive. the bits are set by a low to high trans ition and are cleared by reading the appropriate interrupt source register. 0x15 int_source: system interrupt status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 src_aslp src_fifo src_trans src_lndprt src_pulse src_ff_mt_1 src_ff_mt_2 src_drdy table 17. int_source description int_source description src_aslp auto-sleep/wake interrupt status bit logic ?1? indicates that an interrupt event that can cause a ?wake-to-sleep? or ?sleep-to-w ake? system mode transition has occurred. logic ?0? indicates that no ?wake-to-sl eep? or ?sleep-to-wake? system mode transition interrupt event has occurred. ?wake-to-sleep? transition occurs when no interrupt occurs for a ti me period that exceeds the user specified limit (aslp_count). this causes the system to trans ition to a user specified low odr setting. ?sleep-to-wake? transition occurs when the user s pecified interrupt event has wok en the system; thus causing the system to transition to a us er specified high odr setting. reading the sysmod register clears the src_aslp bit. src_fifo fifo interrupt status bit logic ?1? indicates that a fifo interrupt event such as an ov erflow event or watermark has occurred. logic ?0? indicates that no fifo interrupt event has occurred. fifo interrupt event generators: fifo overflow, or (watermark: f_cnt = f_wmrk) and the interrupt has been enabled. this bit is cleared by readi ng the f_status register. src_trans transient interrupt status bit logic ?1? indicates that an acceleration transient value greater than user spec ified threshold has occurred. logic ?0? indicates that no transient event has occurred. this bit is asserted whenever ? ea ? bit in the trans_src is asserted and the interrupt has been enabled. this bit is cleared by readi ng the trans_src register. src_lndprt landscape/portrait orientation interrupt status bit logic ?1? indicates that an interrupt was generated due to a c hange in the device orientati on status. logic ?0? indicates that no change in orientation status was detected. this bit is asserted whenever ? newlp ? bit in the pl_status is asserted and the interrupt has been enabled. this bit is cleared by readi ng the pl_status register. src_pulse pulse interrupt status bit logic ?1? indicates that an interrupt was generated due to si ngle and/or double pulse event. logic ?0? indicates that no pulse event was detected. this bit is asserted whenever ?ea? bit in the pulse_src is asserted and the interrupt has been enabled. this bit is cleared by reading the pulse_src register. src_ff_mt_1 freefall/motion1 interrupt status bit logic ?1? indicates that the freefall/ motion1 function interrupt is active. logic ?0? indicates that no freefall or motion event was detected. this bit is asserted whenever ?ea? bit in the ff_mt_src_1 register is asserted and the ff_mt interrupt has been enabled. this bit is cleared by reading the ff_mt_src_1 register. src_ff_mt_2 freefall/motion2 interrupt status bit logic ?1? indicates that the freefall/ motion2 function interrupt is active. logic ?0? indicates that no freefall or motion event was detected. this bit is asserted whenever ?ea? bit in the ff_mt_src_2 register is asserted and the ff_mt interrupt has been enabled. this bit is cleared by reading the ff_mt_src_2 register.
sensors 27 freescale semiconductor MMA8450Q 0x16: xyz_data_cfg sensor data configuration register the xyz_data_cfg register configures the 3-axis accele ration data and event flag generator based on the odr. 0x17: hp_filter_cutoff high pass filter register this register sets the high-pa ss filter cut-off frequency for the detection of instantaneous acceleration. the output of this f ilter is indicated by the out_x_delta, out_y_delta, and out_z_de lta registers. the filter cut- off options change based on the data rate selected as shown in ta b l e 1 9 . for details of implementation on the high pass filter, refer to freescale application note an3918. 6.3 portrait/ landscape embedded function registers for more details on the meaning of the diff erent user configurable settings and for ex ample code refer to freescale application note an3915. 0x18: pl_status portrait/landscape status register this status register can be read to get updated information on any change in orientation by reading bit 7, or on the specifics of the orientation by reading bit0 to bit 4. for further under standing of portrait up, portrait down, landscape left, landscape right, back and front please refer to figure 9 src_drdy data ready interrupt bit status logic ?1? indicates that the x,y,z data ready interrupt is acti ve indicating the presence of new data and/or data overrun. otherwise if it is a logic ?0? the x,y,z interrupt is not active. this bit is asserted when the zyxow and/or z yxdr is set and the interrupt has been enabled. this bit is cleared by reading the status and x, y, or z register. 0x16 xyz_data_cfg: sensor data configuration register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fde 0 0 0 0 zdefe ydefe xdefe table 18. xyz_dat a_cfg description fde fifo data output register driver enable. default value: 0. 0: the sample data output registers store the current x, y, & z sample data; 1: the sample data output registers point to the previ ously stored x, y, & z samples data in the fifo buffer. zdefe data event flag enable on new z-axis data. default value: 0 0: event detection disabled; 1: raise event flag on new z-axis data ydefe data event flag enable on new y-axis data. default value: 0 0: event detection disabled; 1: raise event flag on new y-axis data xdefe data event flag enable on new x-axis data. default value: 0 0: event detection disabled; 1: raise event flag on new x-axis data 0x17 hp_filter_cutoff: high pass filter register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 sel1 sel0 table 19. hp_filter_cutoff setting options sel1 sel0 fc (hz) @ odr = 400 hz fc (hz) @ odr = 200 hz fc (hz) @ odr = 100 hz fc (hz) @ odr = 50 hz fc (hz) @ odr = 12.5 hz fc (hz) @ odr = 1.563 hz 0 0 4 2 1 0.5 0.125 0.01 0 1 2 1 0.5 0.25 0.063 0.007 1 0 1 0.5 0.25 0.125 0.031 0.004 1 1 0.5 0.25 0.125 0.062 0.016 0.002 0x18 pl_status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 newlp lo ? lapo[2] lapo[1] lapo[0] bafro[1] bafro[0] table 17. int_source description
sensors freescale semiconductor 28 MMA8450Q newlp is set to 1 whenever a change in lo, bafro, or lapo oc curs. newlp bit is cleared anytime pl_status register is read. 0x19: pl_pre_status portrait/landscape previous data status register this register provides the previous orient ation data from the previous reading. these register definit ions are the same as what has been described in register 0x18. 0x1a: pl_cfg portrait/landscape configuration register this register configures the behavior of the debounce counters and also sets th e landscape/portrait 1g lockout mechanism threshold offset. 0x1b: pl_count portrait landscape debounce register this register sets the debounce counter for the orientation st ate transition. the minimum deb ounce latency is determined by the data rate set by the selected system odr and pl_count re gisters. any change to the odr or device mode transitioning from active to standby or vice versa resets the in ternal landscape/portrait internal debounce counters. the debounce counter scales with the odr, like many of the debounce counters in the other functional blocks. table 22 shows the relationship between the odr, th e step per count and the duration. table 20. pl_status register description newlp landscape-portrait status change flag. default value: 0. 0: no change, 1: bafro and/or lapo and/or z-tilt lockout value has changed lo z-tilt angle lockout. default value: 0. 0: lockout condition has not been detected. 1: z-tilt lockout trip angle has been exceeded. lockout has been detected. bafro[1:0] back or front orientation. default value: 00 00: undefined. this is the default power up state. 01: front: device is in the front facing orientation. 10: back: device is in the back facing orientation. lapo[2:0] (1) landscape/portrait orientation. default value: 000 000: undefined. this is the default power up state. 001: portrait up 010: portrait down 011: landscape right 100: landscape left 1. the default power up state is bafro (undefined), lapo (undefined), and no lockout for orientation function. 0x19 pl_pre_status register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? lo -? lapo[2] lapo[1] lapo[0] bafro[1] bafro[0] 0x1a pl_cfg register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm pl_en ? ? ? goff[2] goff[1] goff[0] table 21. pl_cfg register description dbcntm debounce counter mode selection. default value: 1 0: decrements debounce whenever conditi on of interest is no longer valid. 1: clears counter whenever condition of interest is no longer valid. pl_en portrait-landscape detection enable. default value: 0 0: portrait-landscape detection is disabled. 1: portrait-landscape detection is enabled. goff 1g lockout threshold offset expressed in steps of 50mg. default value: 011 = 1.15g. the offset specified by the goff is added or subtracted from 1g to achieve the optimal 1g lockout threshold. if goff = 011, then the resulting 1g lockout threshold is (1g + 150mg). 000: no offset. 0x1b pl_count register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbnce[7] dbnce[6] dbnce[5] dbnce[4] dbnce[3] dbnce [2] dbnce [1] dbnce [0]
sensors 29 freescale semiconductor MMA8450Q 0x1c: pl_bf_zcomp back/front and z compensation register the z-tilt angle compensation bits allow the user to adjust the z-lockout region from 25 up to 50. the default z-lockout angl e is set to the default value of 32 upon power up. the back to fr ont trip angle is set by default to 75 but this angle also ca n be adjusted from a range of 65 to 80 with 5 step increments. 0x1d - 0x1f: pl_p_l _ths_reg1, 2, 3 portrait-to-l andscape threshold registers the following registers represent the portrait-to-landscape trip threshold registers. these registers are used to set the trip angle for the image transition from the portrait orientation to the landscape orientation. the angle can be selected from ta b l e 2 8 and the corresponding values for that angle should be written into the three pl_p_l_ths registers. table 22. pl_count relationship with the odr output data rate (hz) step duration range 400 2.5 ms 2.5 ms ? 0.637s 200 5 ms 5 ms ? 1.275s 100 10 ms 10 ms ? 2.55s 50 20 ms 20 ms ? 5.1s 12.5 80 ms 80 ms ? 20.4s 1.56 640 ms 640 ms ? 163s 0x1c: pl_bf_zcomp register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bkfr[1] bkfr[0] ? ? ? zlock[2] zlock[1] zlock[0] table 23. pl_bf_zcomp description zlock z-lock angle threshold. range is from 25 to 50. step size is 3.6. default value: 010 32.1 . maximum value: 111 50 . bkfr back front trip angle threshold. default: 10 75. step size is 5. range: (65 to 80). table 24. back/front orientation definitions bkfr back front transition front back transition 00 z < 80 or z > 280 z > 100 and z < 260 01 z < 75 or z > 285 z > 105 and z < 255 10 z < 70 or z > 290 z > 110 and z < 250 11 z < 65 or z > 295 z > 115 and z < 245 0x1d pl_p_l_ths_reg1 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] table 25. pl_p_l_ths_reg1 description p_l_ths portrait-to-landscape threshold register 1. default value: 30 0001_1010 . 0x1e pl_p_l_ths_reg2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] table 26. pl_p_l_ths_reg2 description p_l_ths portrait-to-landscape threshold register 2. default value: 30 0010_0010 . 0x1f pl_p_l_ths_reg3 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0]
sensors freescale semiconductor 30 MMA8450Q 0x20 - 0x22 pl_l_p_ths_reg1, 2, 3 land scape-to-portrait threshold registers the following registers represent the landscape-to-portrait trip th reshold registers. these regist ers are used to set the trip angle for the image transition from the landscape orientation to the portrait orientation. the angle can be selected from ta b l e 3 2 and the corresponding values for that angle should be written into the three pl_l_p_ths registers. table 27. pl_p_l_ths_reg3 description p_l_ths portrait-to-landscape threshold register 3. default value: 30 1101_0100 . table 28. portrait-to-lan dscape trip angle thre sholds look-up table portrait-to-landscape trip angle pl_p_l_ths_reg1 pl_p_l_ths_reg2 pl_p_l_ths_reg3 15 0x17 0x75 0x77 20 0x18 0x14 0x23 25 0x18 0xf3 0x59 30 0x1a 0xa2 0x77 35 0x1b 0x1a 0x1a 40 0x1d 0x92 0x33 45 0x20 0x00 0x00 50 0x23 0x31 0xd9 55 0x27 0x71 0xba 60 0x2d 0x41 0xa2 0x20 pl_l_p_ths_reg1 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] table 29. pl_l_p_ths _reg1 description l_p_ths landscape-to-portrait threshold register 1. default value: 60 0010_1101 . 0x21 pl_l_p_ths_reg2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] table 30. pl_l_p_ths_reg2 description l_p_ths landscape-to-portrait threshold register 2. default value: 60 0100_0001 . 0x22 pl_l_p_ths_reg3 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] table 31. pl_l_p_ths_reg3 description l_p_ths landscape-to-portrait threshold register 3. default value: 60 1010_0010 . table 32. landscape-to-portrait trip angle thresholds look-up table landscape-to-portrait trip angle pl_l_p_ths_reg1 pl_l_p_ths_reg2 pl_l_p_ths_reg3 30 0x1a 0x22 0xd4 35 0x1b 0xa2 0x77 40 0x1d 0x92 0x33 45 0x20 0x00 0x00 50 0x23 0x31 0xd9
sensors 31 freescale semiconductor MMA8450Q 6.4 freefall & motion detection registers for details on how to configure the device for freefall and/or mo tion detection and for sample code, refer to application note an3917. note: there are two freefall and motion detection functions. the r egisters from 0x27 - 0x2a have the same descriptions as registers 0x23 - 0x26. 0x23: ff_mt_cfg_1 freefall and motion configuration register 1 oae bit allows the selection between motion (logical or combinat ion of x, y, z-axis event flags) and freefall (logical and combination of x, y, z-axis event flags) detection. ele denotes whether the enabled event flag will be latched in the ff_mt_src_1 register or the event flag status in the ff_mt_src_1 will indicate the real-time status of the event. if ele bit is set to a lo gic 1, then the event active ?ea? flag is cleared by reading the ff_mt_src_1 source register. zhefe , yhefe , xhefe enables the detection of a high g event when the me asured acceleration data on x, y, or z-axis is higher than the threshold set in ff_mt_ths_1 register. zlefe, ylefe, xlefe enables the detection of a low g event when the measur ed acceleration data on x, y, or z-axis is lower than the threshold set in ff_mt_ths_1 register. ff_mt_ths_1 is the threshold register us ed by the freefall/motion function to detect freefall or motion events. the unsigned 7-bit ff_mt_ths_1 threshold register holds the threshold for the low g event detection where t he magnitude of the x and y and z acceleration values are lower than the threshold value. conver sely the ff_mt_ths_1 also holds the threshold for the high g event detection where the magnitude of the x, or y, or z-ax is acceleration values is higher than the threshold value. 55 0x27 0x71 0xba 60 0x2d 0x41 0xa2 65 0x35 0x91 0x8f 70 0x42 0x31 0x81 75 0x57 0x71 0x77 0x23 ff_mt_cfg_1 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ele oae zhefe zlefe yhefe ylefe xhefe xlefe table 33. ff_mt_cfg_1 description ele event latch enable: event flag is latched into ff_mt_src_1 register. reading of the ff_mt_src_1 register clears the ea event flag. default value: 0 0: event flag latch disabled; 1: event flag latch enabled oae logical or/and combination of events flags. default value: 0 0: logical and combination of events flags; 1: logical or combination of events flags zhefe event flag enable on z high event. default value: 0 0: event detection disabled; 1: event detection enabled zlefe event flag enable on z low event. default value: 0 0: event detection disabled; 1: event detection enabled yhefe event flag enable on y high event. default value: 0 0: event detection disabled; 1: event detection enabled ylefe event flag enable on y low event. default value: 0 0: event detection disabled; 1: event detection enabled xhefe event flag enable on x high event. default value: 0 0: event detection disabled; 1: event detection enabled xlefe event flag enable on x low event. default value: 0 0: event detection disabled; 1: event detection enabled table 32. landscape-to-portrait trip angle thresholds look-up table
sensors freescale semiconductor 32 MMA8450Q 0x24 ff_mt_src_1 register this register keeps track of the acceleration event which is tr iggering (or has triggered, in case of ele bit in ff_mt_cfg_1 register being set to 1) the event flag. in particular ea is se t to a logic 1 when the logical combination of acceleration even ts flags specified in ff_mt_cfg_1 register is true. this bit is us ed in combination with the values in int_en_ff_mt_1 and int_cfg_ff_mt_1 register to generate the freefall/motion interrupts. an x,y, or z high or an x,y, and z high event is true when th e acceleration value of the x or y or z axes is higher than the preset threshold value defined in the ff_mt_ths_1 register. conversely x,y, or z high or an x,y, and z low event is true when the acceleration value of the x and y and z axes are lower than the preset threshold value defined in the ff_mt_ths_1 register. when the ele bit is set, only the ea bit is latched. the other bits are not latched. to see the events t hat have been detected, the register must be read immediately. the ea bit will remain high until the source register is read. 0x25: ff_mt_ths_1 freefall and motion threshold 1 register the minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range of 0 to 127. therefore: ? if the selected acceleration g range is 8g mode (fs = 11), the minimum threshold resolution is 0.063g/lsb. the maximum value is 8g. ? if the selected acceleration g range is 4g mode (fs = 10), the minimum threshold resolution is 0.0315g/lsb. the maximum value is 4g. ? if the selected acceleration g range is 2g mode (fs = 01), the minimum threshold resolution is 0.01575g/lsb. the maximum value is 2g. when dbcntm bit is a logic ?1?, the debounce counter is clear ed to 0 whenever the event of interest is no longer true ( figure 12 part b) while if the dbcntm bit is set a logic ?0? the debounce co unter is decremented by 1 whenever the event of interest is no longer true ( figure 12 part c) until the debounce counter reaches 0 or the event of interest becomes active. decrementing of the deb ounce counter acts as a median filt er enabling the system to filter ou t irregular spurious events which might impede the detection of the event. 0x24: ff_mt_src_ freefall and motion source register (0x24) (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ea zhe zle yhe yle xhe xle table 34. ff_mt_src_1 description ea event active flag. default value: 0 0: no event flag has been asserted; 1: one or more event flags have been asserted. zhe z high event flag. default value: 0 0: no z high event detected, 1: z high event has been detected zle z low event flag. default value: 0 0: no z low event detected, 1: z low event has been detected yhe y high event flag. default value: 0 0: no y high event detected, 1: y high event has been detected yle y low event flag. default value: 0 0: no y low event detected, 1: y low event has been detected xhe x high event flag. default value: 0 0: no x high event detected, 1: x high event has been detected xle x low event flag. default value: 0 0: no x low event detected, 1: x low event has been detected 0x25 ff_mt_ths_1 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 35. ff_mt_ths_1 description dbcntm debounce counter mode selection. default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. ths[6:0] freefall /motion threshold: default value: 000 0000
sensors 33 freescale semiconductor MMA8450Q figure 12. dbcntm bit function 0x26: ff_mt_count_1 freefall motion count 1 register this register sets the number of debounce sample counts for the event trigger. d7 - d0 define the number of debounce sample counts for the event trigger. when the debounce counter exceeds the ff_mt_count_1 value, a freefall/motion event flag is set. the time step used for the debounce sample count depends on the odr chosen ( ta b l e 3 7 ). an odr of 100 hz and a ff_mt_count_1 value of 15 wo uld result in a debounce response time of 150 ms. 0x26 ff_mt_count_1 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 36. ff_mt_co unt_1 description d[7-0] count value. default value: 0000_0000 table 37. ff_mt_count_1 and ff_mt_count_2 relationship with the odr output data rate (hz) step duration range 400 2.5 ms 2.5 ms ? 0.63s 200 5 ms 5 ms ? 1.275s 100 10 ms 10 ms ? 2.55s 50 20 ms 20 ms ? 5.1s 12.5 80 ms 80 ms ? 20.4s 1.56 640 ms 640 ms ? 163s low g event on count threshold ff_mt ea ff all 3-axis (freefall) counter value low g event on count threshold ff_mt (a) all 3-axis (freefall) counter value low g event on count threshold ff_mt ea ff all 3-axis (freefall) counter value dbcntm = 1 (b) ea ff dbcntm = 0 (c)
sensors freescale semiconductor 34 MMA8450Q 0x27: ff_mt_cfg_2 freefall and motion configuration 2 register these registers all have the same descriptions as above for registers 0x23 - 0x26. 0x28: ff_mt_src_2 freefall and motion source 2 register 0x29: ff_mt_ths_2 freefall and motion threshold 2 register 0x2a: ff_mt_count_2 freefall and motion debounce 2 register 6.5 transient detection registers for more information on the uses of the transient func tion and sample code, refer to application note an3918. 0x2b: transient_cfg transient configuration register the transient detection mechanism can be configured to raise an interrupt when the magnitude of the high pass filtered data is greater than a user definable threshold. the transient_cfg register is used to enable the transient interrupt generation mechanism for each of the 3 axes (x, y, z) of acceleration. 0x2c: transient_src transient source register the transient source register is read to determine the source of an interrupt. when the ele bit is set in register0x2b the ?ea? event active bit in the source register is latched. the other bi ts in the source register are not latched. the source register must be read immediately following the interrupt to determine the axes the event occurred on. 0x27 ff_mt_cfg_2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 ele oae zhefe zlefe yhefe ylefe xhefe xlefe 0x28 ff_mt_src_2 register (read only) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 ? ea zhe zle yhe yle xhe xle 0x29 ff_mt_ths_2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 th s4 ths3 ths2 ths1 ths0 0x2a ff_mt_count_2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 0x2b transient_ cfg register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 ????eleztefeytefextefe table 38. transient_ cfg description ele transient event flag is latched into the transient_src register . reading of the transient_src register clears the event flag. default value: 0 0: event flag latch disabl ed; 1: event flag latch enabled ztefe event flag enable on z-axis. default value: 0 0: event detection disabled; 1: event detection enabled ytefe event flag enable on y-axis. default value: 0 0: event detection disabled; 1: event detection enabled xtefe event flag enable on x-axis. default value: 0 0: event detection disabled; 1: event detection enabled 0x2c transient_src register (read only) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? ea ztranse ytranse xtranse
sensors 35 freescale semiconductor MMA8450Q 0x2d: transient_ths transient threshold register the transient_ths register sets the threshold limit for the high pass filtered acceleration. the value in the transient_ths register corresponds to a g value which is co mpared against the values of out_x_delta, out_y_delta, and out_z_delta. if the acceleration exceeds the threshold limit an event flag is raised and an interrupt is generated if interrupts are enabled. the minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range of 0 to 127. therefore: ? if the selected acceleration g range is 8g mode (fs = 11), the minimum threshold resolution is 0.063g/lsb. the maximum is 8g. ? if the selected acceleration g range is 4g mode (fs = 10), the minimum threshold resolution is 0.0315g/lsb. the maximum is 4g. ? if the selected acceleration g range is 2g mode (fs = 01), the minimum threshold resolution is 0.01575g/lsb. the maximum is 2g. ? the dbcntm bit behaves in the same manner de scribed previously for the motion/freefall 1. 0x2e: transient_count transient debounce register the transient_count sets the minimum number of debounce counts continuously matching the condition where the unsigned value of out_x_delta or out_y_delta or out_z_delt a register is greater than the user specified value of transient_ths. the time step for the transient detection debounce co unter is set by the value of the system odr. an odr of 100 hz and a transient_co unt value of 15 would result in a debounce response time of 150 ms. table 39. transient_src description ea event active flag. default value: 0 0: no event flag asserted; 1: one or more event flag has been asserted. ztranse z transient event. default value: 0 0: no z event detected, 1: z event detected ytranse y transient event. default value: 0 0: no y event detected, 1: y event detected xtranse x transient event. default value: 0 0: no x event detected, 1: x event detected 0x2d transient_ths register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 dbcntm ths6 ths5 th s4 ths3 ths2 ths1 ths0 table 40. transient _ths description dbcntm debounce counter mode selection. default value: 0 0: in crements or decrements debounce; 1: increments or clears counter ths[6:0] transient threshold: default value: 000_0000 0x2e transient_count register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 41. transient _count description d[7-0] count value. default value: 0000_0000 table 42. transient_count relationship with the odr output data rate (hz) step duration range 400 2.5 ms 2.5 ms ? 0.637s 200 5 ms 5 ms ? 1.275s 100 10 ms 10 ms ? 2.55s 50 20 ms 20 ms ? 5.1s 12.5 80 ms 80 ms ? 20.4s 1.56 640 ms 640 ms ? 163s
sensors freescale semiconductor 36 MMA8450Q 6.6 tap detection registers for more details of how to configure the tap detection and sa mple code please refer to freescale application note, an3919. the tap detection registers are referred to as ?pulse?. 0x2f: pulse_cfg pulse configuration register this register configures the event flag for the tap detection for enabling/disabling the detection of a single and double pulse on each of the axes. 0x30: pulse_src pulse source register this register indicates a double or single pulse event has occurred. the corresponding axis and event must be enabled in register 0x2f for the event to be seen in the source register. 0x2f pulse_cfg register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 dpa ele zdpefe zspefe ydpefe yspefe xdpefe xspefe table 43. pulse_cfg description dpa double pulse abort. 0: double pulse detection is not aborted if the start of a pulse is detected during the time period specified by the pulse_ltcy register. 1: setting the dpa bit momentarily suspends the double tap detecti on if the start of a pulse is detected during the time period specified by the pulse_ltcy register and the pulse ends before the end of the time period specified by the pulse_ltcy register. ele pulse event flags are latched into the pulse_src register. reading of the pulse_src register clears the event flag. default value: 0 0: event flag latch disabled ; 1: event flag latch enabled zdpefe event flag enable on double pulse even t on z-axis. default value: 0 0: event detection disabled; 1: event detection enabled zspefe event flag enable on single pulse ev ent on z-axis. default value: 0 0: event detection disabled; 1: event detection enabled ydpefe event flag enable on double pulse even t on y-axis. default value: 0 0: event detection disabled; 1: event detection enabled yspefe event flag enable on single pulse ev ent on y-axis. default value: 0 0: event detection disabled; 1: event detection enabled xdpefe event flag enable on double pulse even t on x-axis. default value: 0 0: event detection disabled; 1: event detection enabled xspefe event flag enable on single pulse ev ent on x-axis. default value: 0 0: event detection disabled; 1: event detection enabled 0x30 pulse_src register (read only) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 ? ea zdpe zspe ydpe yspe xdpe xspe table 44. tpulse_src description ea event active flag. default value: 0 0: no event flag has been asserted; 1: one or more events have been asserted zdpe double pulse on z-axis event. default value: 0 0: no event detected; 1: double z event detected zspe single pulse on z-axis event. default value: 0 0: no event detected; 1: single z event detected ydpe double pulse on y-axis event. default value: 0 0: no event detected; 1: double y event detected yspe single pulse on y-axis event. default value: 0 0: no event detected; 1: single y event detected xdpe double pulse on x-axis event. default value: 0 0: no event detected; 1: double x event detected xspe single pulse on x-axis event. default value: 0 0: no event detected; 1: single x event detected
sensors 37 freescale semiconductor MMA8450Q 0x31 - 0x33: pulse_thsx, y, z pulse threshold for x, y & z registers the pulse threshold can be set separately for the x, y and z axes . the threshold values range from 0 to 31 counts with steps of 0.258g/lsb at a fixed 8g acceleration range , thus the minimum resolution is always fixed at 0.258g/lsb irrespective of the selected g range. the pulse_thsx, pulse_thsy and pulse_thsz registers define the threshold which is used by the system to start the pulse detection procedure. the threshold value is expressed over 5-bits as an unsigned number. 0x34: pulse_tmlt pulse time window 1 register the bits tmlt7 through tmlt0 def ine the maximum time interval that can elapse between the start of the acceleration on the selected axis exceeding the specified th reshold and the end when the acceleration on the selected axis must go below the specified threshold to be considered a valid pulse. the minimum time step for the pulse time limit is defined in table 48 . maximum time for a given odr is the minimum time step at the given power mode multiplied by 255. the time steps available are dependent on whether the device is in normal power mode or in low power mode. notice in the table below th at the time step is twice as long in low power mode. therefore an odr setting of 400 hz with normal power mode woul d result in a maximum pulse time limit of (0.625 ms * 255) 159 ms. 0x31 pulse_thsx register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thsx4 thsx3 thsx2 thsx1 thsx0 table 45. pulse_thsx description thsx4, thsx0 pulse threshold on x-axis. default value: 0_0000 0x32 pulse_thsy register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thsy4 thsy3 thsy2 thsy1 thsy0 table 46. pulse_thsy description thsy4, thsy0 pulse threshold on y-axis. default value: 0_0000 0x33 pulse_thsz register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thsz4 thsz3 thsz2 thsz1 thsz0 table 47. pulse_thsz description thsz4, thsz0 pulse threshold on z-axis. default value: 0_0000 0x34 pulse_tmlt register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmlt7 tmlt6 tmlt5 tmlt4 tmlt3 tmlt2 tmlt1 tmlt0 table 48. time step for pulse time limit at odr and power mode output data rate (hz) step at normal mode step at low power mode 400 0.625 ms 1.25 ms 200 1.25 ms 2.5 ms 100 2.5 ms 5.0 ms 50 5 ms 10 ms 12.5 5 ms 10 ms 1.56 5 ms 10 ms
sensors freescale semiconductor 38 MMA8450Q 0x35: pulse_ltcy pulse latency timer register the bits ltcy7 through ltcy0 define the time interval that star ts after the first pulse detection. during this time interval, a ll pulses are ignored. note: this timer must be set for single pulse and for double pulse. the minimum time step for the pulse latency is defined in table 49 . the maximum time is the time step at the odr and power mode multiplied by 255. notice that the time step is twice the duration if the device is operating in low power mode, as shown below. 0x36: pulse_wind second pulse time window register the bits wind7 through wind0 define the maximum interval of time th at can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. the detected second pulse width must be shorter than the time limi t constraints specified by the pulse_tmlt register, but the end of the double pulse need not finish within the time specified by the pulse_wind register. the minimum time step for the pulse window is defined in ta b l e 5 0 . the maximum time is the time step at the odr and power mode multiplied by 255. 6.7 auto-sleep registers for additional information on how to configure the devic e for the auto-sleep/wake feature, refer to an3921. 0x37: aslp_count auto-sleep inactivity timer register the aslp_count register sets the minimum time period of i nactivity required to change current odr value from the value specified in the dr[2:0] to aslp_rate (reg 0x38) value provided the slpe bit is set to a logic ?1? in the ctrl_reg2 register. 0x35 pulse_ltcy register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ltcy7 ltcy6 ltcy5 ltcy4 ltcy3 ltcy2 ltcy1 ltcy0 table 49. time step for pulse latency at odr and power mode output data rate (hz) step at normal mode step at low power mode 400 1.25 ms 2.5 ms 200 2.5 ms 5.0 ms 100 5.0 ms 20 ms 50 10 ms 20 ms 12.5 10 ms 20 ms 1.56 10 ms 20 ms 0x36 pulse_wind register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wind7 wind6 wind5 wind4 wind3 wind2 wind1 wind0 table 50. time step for pulse detection window at odr and power mode output data rate (hz) step at normal mode step at low power mode 400 1.25 ms 2.5 ms 200 2.5 ms 5.0 ms 100 5.0 ms 20 ms 50 10 ms 20 ms 12.5 10 ms 20 ms 1.56 10 ms 20 ms 0x37 aslp_count register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 51. aslp_count description d[7-0] duration value. default value: 0000 0000
sensors 39 freescale semiconductor MMA8450Q d7-d0 defines the minimum duration time to change current odr value from dr to aslp_rate . time step and maximum value depend on the odr chosen (see ta b l e 5 2 ). in order to wake the device, the desired function or functions must be enabled an d set to ?wake from sleep?. all enabled functions will still function in sleep mode at the sleep odr. only the functions that have been sele cted for ?wake from sleep? will wake the device. MMA8450Q has 6 functions that can be used to keep the sensor from falling asleep namely, transient, orientation, tap, motion/ff1 and motion/ff2 and the fifo. one or more of these f unctions can be enabled. in order to wake the device, functions are provided namely, transient, orientation, tap, and the two moti on/freefall. note that the fifo does not wake the device. the auto-wake/sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. the fifo gate (bit 7) in register 0x3a, when set, will hold the last data in the fifo before transit ioning to a different odr. after the buffer is flushed, it wi ll accept new sample data at the current odr. see r egister 0x3a for the wake from sleep bits. if the auto-sleep bit is disabled, then the device can only to ggle between standby and wake mode by writing to the fs0 and fs1 bits in register 0x38 ctrl reg1. if auto-sleep interrupt is enabled, transitioning from active mode to auto-sleep mode and vice versa generates an interrupt. 0x38: ctrl_reg1 system control 1 register it is important to note that when the device is in auto-sle ep mode, the system odr and the data rate for all the system functional blocks are overwritten by the data rate set by the aslp_rate field in register 0x38. dr[2:0] bits select the output data rate (odr) for acceleration samples. the default value is 000 for a data rate of 400 hz. table 52. aslp_count relationship with odr output data rate (odr) duration step 400 0 to 81s 320 ms 200 0 to 81s 320 ms 100 0 to 81s 320 ms 50 0 to 81s 320 ms 12.5 0 to 81s 320 ms 1.56 0 to 325.125s 640 ms 0x38 ctrl_reg1 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 aslp_rate1 aslp_rate0 0 dr2 dr1 dr0 fs1 fs0 table 53. ctrl_reg1 description aslp_rate [1:0] this register configures the auto-wake samp le frequency when the device is in sleep mode. see table 54 for more information. dr[2:0] data rate selection. default value: 000 fs[1:0] full scale selection. default value: 00 (00: standby mode; 01: active mode 2g; 10: active mode 4g; 11: active mode 8g) table 54. sleep mode poll rate description aslp_rate1 aslp_rate0 frequency (hz) 0 0 50 0 1 25 1 0 12.5 1 1 1.56 table 55. system output data rate selection dr2 dr1 dr0 output data rate (odr) time between data samples 0 0 0 400 hz 2.5 ms 0 0 1 200 hz 5 ms
sensors freescale semiconductor 40 MMA8450Q fs[1:0] bits select between standby mode and active mode. the default value is 00 for standby mode. 0x39: ctrl_reg2 system control 2 register st bit activates the self-test function. when st is set to one, an output change will occur to the device outputs (refer to ta b l e 2 and table 3 ) thus allowing host application to check th e functionality of the entire signal chain. boot bit is used to activate the software reset. the boot mechanism can be enabled in standby and active mode. when the boot bit is enabled the boot mechanism resets all functional block registers and loads the respective internal registers with default nvm values. the system will automatically tr ansition to standby mode if not already in st andby mode before the software reset (re-boot process) can occur. note : the i 2 c communication system is re set to avoid accidental corrupted data access. 0x3a: ctrl_reg3 interrupt control register 0 1 0 100 hz 10 ms 0 1 1 50 hz 20 ms 1 0 0 12.5 hz 80 ms 1 0 1 1.563 hz 640 ms table 56. full scale selection fs1 fs0 mode g range 0 0 standby ? 0 1 active 2g 1 0 active 4g 1 1 active 8g 0x39 ctrl_reg2 register (read/write) bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 st boot 0 0 0 0 slpe mods table 57. ctrl_reg2 description st self-test enable. default value: 0 0: self-test disabled; 1: self-test enabled boot reboot device content (software reset). default value: 0 0: device reboot disabled; 1: device reboot enabled. slpe (1) 1. when slpe = 1, the transitioning between sleep mode and wake mode results in a fifo flush and a reset of internal functional bl ock counters. all functional block status information are preserve except otherwise stated. see table 58 for more information about the fifo_gate bit in ctrl_reg3 register. auto-sleep enable. default value: 0 0: auto-sleep is not enabled; 1: auto-sleep is enabled. mods low power mode / normal mode selection. default value: 0 0: normal mode; 1: low power mode. 0x3a ctrl_reg3 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo_gate wake_trans wake_lndprt wake_pul se wake_ff_mt_1 wake_ff_mt_2 ipol pp_od table 55. system output data rate selection
sensors 41 freescale semiconductor MMA8450Q ipol bit selects the polarity of the interrupt signal. when ipol is ?0? any interrupt event will signalled with a logical 0. pp_od bit configures the interrupt pin to push-pull or in op en drain mode. the open drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. 0x3c: ctrl_reg5 register (read/write) table 58. ctrl_reg3 description fifo_gate 0: fifo gate is bypassed. fifo is flushed upon the system mode transitioning from wake-to-sleep mode or from sleep-to- wake mode. 1: the fifo input buffer is blocked when transitioning from ?wake-to-sleep? mode or from ?sleep-to-wake? mode until the fifo is flushed. although the system transitions from ?wake-to-sleep? or from ?sleep-to-wake? the contents of the fifo buffer are preserved, new data samples are ignored unt il the fifo is emptied by the host application. if the fifo_gate bit is set to logic 1 and the fifo buffer is not emptied before the arrival of the next sample, then the fgerr bit in the sys_mod register (0x14) will be asserted. the fgerr bit remains asserted as long as the fifo buffer remains un-emptied. emptying the fifo buffer clears the fgerr bit in the sys_mod register. wake_trans 0: transient function is bypassed in sleep mode 1: transient function interrupt can wake up system wake_lndprt 0: orientation function is bypassed in sleep mode 1: orientation function interrupt can wake up system wake_pulse 0: pulse function is bypassed in sleep mode 1: pulse function interrupt can wake up system wake_ff_mt_1 0: freefall/motion1 functi on is bypassed in sleep mode 1: freefall/motion1 function interrupt can wake up wake_ff_mt_2 0: freefall/motion2 functi on is bypassed in sleep mode 1: freefall/motion2 function interrupt can wake up system ipol interrupt polarity active high, or active low. default value 0. 0: active low; 1: active high pp_od push-pull/open drain selection on interrupt pad. default value 0. 0: push-pull; 1: open drain 0x3c ctrl_reg5 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_en_aslp int_en_fifo int_en_trans int_en_lndprt in t_en_pulse int_en_ff_mt_1 int_en_ff_mt_2 int_en_drdy table 59. interrupt enable register description interrupt enable description int_en_aslp interrupt enable. default value: 0 0: auto-sleep/wake interrupt disabled; 1: auto-sleep/wake interrupt enabled. int_en_fifo interrupt enable. default value: 0 0: fifo interrupt disabled; 1: fifo interrupt enabled. int_en_trans interrupt enable. default value: 0 0: transient interrupt disabled; 1: transient interrupt enabled. int_en_lndprt interrupt enable. default value: 0 0: orientation (landscape/portrait) interrupt disabled. 1: orientation (landscape/portrait) interrupt enabled. int_en_pulse interrupt enable. default value: 0 0: pulse detection interrupt disabled; 1: pulse detection interrupt enabled int_en_ff_mt_1 interrupt enable. default value: 0 0: freefall/motion1 interrupt disabled; 1: freefall/motion1 interrupt enabled int_en_ff_mt_2 interrupt enable. default value: 0 0: freefall/motion2 interrupt disabled; 1: freefall/motion2 interrupt enabled int_en_drdy interrupt enable. default value: 0 0: data ready interrupt disabled; 1: data ready interrupt enabled
sensors freescale semiconductor 42 MMA8450Q the corresponding functional block interrupt enable bit allows t he functional block to route its event detection flags to the system?s interrupt controller. th e interrupt controller routes the enabled functional block interrupt to the int1 or int2 pin. 0x3c: ctrl_reg5 interrupt configuration register the system?s interrupt controller shown in figure 10 uses the corresponding bit field in the ctrl_reg5 register to determine the routing table for the int1 and int2 interrupt pins. if the bi t value is logic ?0? the functional block?s interrupt is route d to int2, and if the bit value is logic ?1? then the interrupt is routed to int1. one or more functions can assert an interrupt pin; ther efore a host application responding to an interrupt should read the in t_source (0x15) register to det ermine the appropriate sources of the interrupt. 6.8 user offset correction registers for more information on how to calibrate the 0g offset re fer to an3916 offset calibration using the MMA8450Q. the 2?s complement offset correction registers values are used to reali gn the zero g position of the x, y, and z-axis after device boar d mount. the resolution of the offset regist ers is 3.906 mg per lsb. the 2?s complement 8-bit value would result in an offset compensation range 0.5g. 0x3d: off_x offset correction x register 0x3e: off_y offset correction y register 0x3f: off_z offset correction z register 0x3c ctrl_reg5 register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndprt in t_cfg_pulse int_cfg_ff_mt_1int_cfg_ff_mt_2 int_cfg_drdy table 60. interrupt configuration register description interrupt configuration description int_cfg_aslp int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_fifo int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_trans int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_lndprt int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_pulse int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_ff_mt_1 int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_ff_mt_2 int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin int_cfg_drdy int1/int2 configuration. default value: 0 0: interrupt is routed to int2 pin; 1: interrupt is routed to int1 pin 0x3d off_x register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 61. off_x description d7-d0 x -axis offset trim lsb value. default value: 0000_0000. 0x3e off_y register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 62. off_y description d7-d0 y-axis offset trim lsb value. default value: 0000_0000. 0x3f off_z register (read/write) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 table 63. off_z description d7-d0 z-axis offset trim lsb value. default value: 0000_0000.
sensors 43 freescale semiconductor MMA8450Q appendix a table 64. MMA8450Q register map reg name definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 status data status r zyxow zow yow xow zyxdr zdr ydr xdr 01 out_x_msb 8-bit x data r xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 02 out_y_msb 8-bit y data r yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 03 out_z_msb 8-bit z data r zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4 04 status data status r zyxow zow yow xow zyxdr zdr ydr xdr 05 out_x_lsb 12-bit x data r 0 0 0 0 xd3 xd2 xd1 xd0 06 out_x_msb 12-bit x data r xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 07 out_y_lsb 12-bit y data r 0 0 0 0 yd3 yd2 yd1 yd0 08 out_y_msb 12-bit y data r yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 09 out_z_lsb 12-bit z data r 0 0 0 0 zd3 zd2 zd1 zd0 0a out_z_msb 12-bit z data r zd11 zd10 zd9 zd8 zd7 zd6 zd5 zd4 0b status data status r zyxow zow yow xow zyxdr zdr ydr xdr 0c out_x_delta 8-bit transient x data r xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 0d out_y_delta 8-bit transient y data r yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 0e out_z_delta 8-bit transient z data r zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 0f who_am_i id register r ? ? ? ? ? ? ? ? 10 f_status fifo status r f_ovf f_wmrk_flag f_cnt5 f_cnt4 f_cnt3 f_cnt2 f_cnt1 f_cnt0 11 f_8data 8-bit fifo data r xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 12 f_12data 12-bit fifo data r 0 0 0 0 xd3 xd2 xd1 xd0 13 f_setup fifo setup r/w f_mode1 f_mode0 f_wmrk5 f_wmrk4 f_wmrk3 f_wmrk2 f_wmrk1 f_wmrk0 14 sysmod system mode r perr fgerr 0 0 0 0 sysmod1 sysmod0 15 int_source interrupt status r src_aslp src_fifo src_tr ans src_lndprt src_pulse src_ff_mt_1 src_ff_mt_2 src_drdy 16 xyz_data_cfg data config. r/w fde 0 0 0 ? zdefe ydefe xdefe 17 hp_filter_cutoff hp filter setting r/w 0 0 0 0 0 0 sel1 sel0 18 pl_status pl status r newlp lo - lapo[2] lapo[1] lapo[0] bafro[1] bafro[0] 19 pl_pre_status previous pl status r - lo - lapo[2] lapo[1] lapo[0] bafro[1] bafro[0] 1a pl_cfg pl configuration r/w dbcntm pl_en - - - goff[2] goff[1] goff[0] 1b pl_count pl debounce r/w dbnce[7] dbnce[6] dbnce[5 ] dbnce[4] dbnce[3] dbnce [2] dbnce [1] dbnce [0] 1c pl_bf_zcomp pl back/front and z compensation r/w bkfr[1] bkfr[0] - - - zlock[2] zlock[1] zlock[0] 1d pl_p_l_ths_reg1 portrait-to-landscape threshold setting 1 r/w p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] 1e pl_p_l_ths_reg2 portrait-to-landscape threshold setting 2 r/w p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] 1f pl_p_l_ths_reg3 portrait-to-landscape threshold setting 3 r/w p_l_ths[7] p_l_ths[6] p_l_ths[5] p_l_ths[4] p_l_ths[3] p_l_ths[2] p_l_ths[1] p_l_ths[0] 20 pl_l_p_ths_reg1 landscape-to-portrait threshold setting 1 r/w l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] 21 pl_l_p_ths_reg2 landscape-to-portrait threshold setting21 r/w l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] 22 pl_l_p_ths_reg3 landscape-to-portrait threshold setting 3 r/w l_p_ths[7] l_p_ths[6] l_p_ths[5] l_p_ths[4] l_p_ths[3] l_p_ths[2] l_p_ths[1] l_p_ths[0] 23 ff_mt_cfg_1 ff/motion config. 1 r/w ele oae zhefe zlefe yhefe ylefe xhefe xlefe 24 ff_mt_src_1 ff/motion source 1 r ? ea zhe zle yhe yle xhe xle 25 ff_mt_ths_1 ff/motion threshold 1 r/w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 26 ff_mt_count_1 ff/motion debounce 1 r/w d7 d6 d5 d4 d3 d2 d1 d0 27 ff_mt_cfg_2 ff/motion config. 2 r/w e le oae zhefe zlefe yhefe ylefe xhefe xlefe 28 ff_mt_src_2 ff/motion source 2 r ? ea zhe zle yhe yle xhe xle
sensors freescale semiconductor 44 MMA8450Q 29 ff_mt_ths_2 ff/motion threshold 2 r/w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 2a ff_mt_count_2 ff/motion debounce 2 r/w d7 d6 d5 d4 d3 d2 d1 d0 2b transient_cfg transient config. r/w ? ? ? ? ele ztefe ytefe xtefe 2c transient_src transient source r ? ? ? ? ea ztranse ytranse xtranse 2d transient_ths transient threshold r/w dbcntm ths6 ths5 ths4 ths3 ths2 ths1 ths0 2e transient_count transient debounce r/w d7 d6 d5 d4 d3 d2 d1 d0 2f pulse_cfg pulse config. r/w dpa ele zdpefe zspefe ydpefe yspefe xdpefe xspefe 30 pulse_src pulse source r ? ea zdpe zspe ydpe yspe xdpe xspe 31 pulse_thsx pulse x threshold r/w 0 0 0 thsx4 thsx3 thsx2 thsx1 thsx0 32 pulse_thsy pulse y threshold r/w 0 0 0 thsy4 thsy3 thsy2 thsy1 thsy0 33 pulse_thsz pulse z threshold r/w 0 0 0 thsz4 thsz3 thsz2 thsz1 thsz0 34 pulse_tmlt pulse first timer r/w tmlt7 tmlt6 tmlt5 tmlt4 tmlt3 tmlt2 tmlt1 tmlt0 35 pulse_ltcy pulse latency r/w ltcy7 ltcy6 ltcy5 ltcy4 ltcy3 ltcy2 ltcy1 ltcy0 36 pulse_wind pulse 2nd window r/w wind7 wind6 wind5 wind4 wind3 wind2 wind1 wind0 37 aslp_count auto-sleep counter r/w d7 d6 d5 d4 d3 d2 d1 d0 38 ctrl_reg1 control reg 1 r/w asl p_rate1 aslp_rate0 0 dr2 dr1 dr0 fs1 fs0 39 ctrl_reg2 control reg 2 r/w st rst 0 0 0 0 slpe mods 3a ctrl_reg3 control reg3 r/w (wake interrupts from sleep) fifo_gate wake_trans wake_lndprt wake_pulse wake_ff_mt_1 wake_ff_mt_2 ipol pp_od 3b ctrl_reg4 control reg4 r/w (interrupt enable map) int_en_aslp int_en_fifo int_en_trans int_en_lndprt in t_en_pulse int_en_ff_mt_1 int_en_ff_mt_2 int_en_drdy 3c ctrl_reg5 control reg5 r/w (interrupt configuration) int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndprt in t_cfg_pulse int_cfg_ff_mt_1 int_cfg_ff_mt_2 int_cfg_drdy 3d off_x x 8-bit offset d7 d6 d5 d4 d3 d2 d1 d0 3e off_y y 8-bit offset d7 d6 d5 d4 d3 d2 d1 d0 3f off_z z 8-bit offset d7 d6 d5 d4 d3 d2 d1 d0 table 64. MMA8450Q register map
sensors 45 freescale semiconductor MMA8450Q table 65. accelero meter output data 12-bit data range 2g range 4g range 8g 0111 1111 1111 1.999g +3.998g +7.996g 0111 1111 1110 1.998g +3.996g +7.992g ? ? ? ? 0000 0000 0001 0.001g +0.002g +0.004g 0000 0000 0000 0.000g 0.000g 0.000g 1111 1111 1111 -0.001g -0.002g -0.004g ? ? ? ? 1000 0000 0001 -1.999g -3.998g -7.996g 1000 0000 0000 -2.000g -4.000g -8.000g 8- bit data range 2g range 4g range 8g 0111 1111 1.984g +3.968g +7.936g 0111 1110 1.968g +3.936g +7.872g ? ? ? ? 0000 0001 +0.016g +0.032g +0.064g 0000 0000 0.000g 0.000g 0.000g 1111 1111 -0.016g -0.032g -0.064g ? ? ? ? 1000 0001 -1.984g -3.968g -7.936g 1000 0000 -2.000g -4.000g -8.000g
sensors freescale semiconductor 46 MMA8450Q appendix b figure 13. distribution of pre board mounted devices tested in sockets (1 count = 3.9 mg)
sensors 47 freescale semiconductor MMA8450Q figure 14. distribution of post boar d mounted devices (1 count = 3.9 mg)
sensors freescale semiconductor 48 MMA8450Q figure 15. 8g x-axis tcs
sensors 49 freescale semiconductor MMA8450Q figure 16. 8g y-axis tcs
sensors freescale semiconductor 50 MMA8450Q figure 17. 8g z-axis tcs
sensors 51 freescale semiconductor MMA8450Q figure 18. 8g x-axis tco (mg/c)
sensors freescale semiconductor 52 MMA8450Q figure 19. 8g y-axis tco (mg/c)
sensors 53 freescale semiconductor MMA8450Q figure 20. 8g z-axis tco (mg/c)
sensors freescale semiconductor 54 MMA8450Q package dimensions case 2077-01 issue o 16-lead qfn
sensors 55 freescale semiconductor MMA8450Q package dimensions case 2077-01 issue o 16-lead q
sensors freescale semiconductor 56 MMA8450Q package dimensions case 2077-01 issue o 16-lead q
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